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VLSI Design Methodology Development, First Edition
book

VLSI Design Methodology Development, First Edition

by Thomas Dillinger
June 2019
Intermediate to advanced content levelIntermediate to advanced
752 pages
22h 19m
English
Pearson
Content preview from VLSI Design Methodology Development, First Edition

Chapter 20. Preparation for Tapeout

20.1 Introduction to Tapeout Preparation

This brief chapter summarizes the SoC project manager and methodology team tasks required in preparation for tapeout data release to the foundry. Many of these tasks have been introduced in previous sections; this chapter consolidates those earlier discussions.

It is common for an SoC project manager to be responsible for capturing design status information into a tapeout checklist. To assist with this task, the SoC methodology and CAD teams will have developed and maintained a methodology manager application—often referred to as the project scoreboard—which records design checking and analysis flow results for the SoC model hierarchy and successive model version releases. ...

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Publisher Resources

ISBN: 9780135657645