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VLSI Design Methodology Development, First Edition
book

VLSI Design Methodology Development, First Edition

by Thomas Dillinger
June 2019
Intermediate to advanced content levelIntermediate to advanced
752 pages
22h 19m
English
Pearson
Content preview from VLSI Design Methodology Development, First Edition

Chapter 21. Post-Silicon Debug and Characterization (“Bring-up”) and Product Qualification

21.1 Systematic Test Fails

During wafer testing, the set of failing dies may indicate that a systematic defect is present. As described in Section 19.7, test diagnostic procedures are pursued in an attempt to localize and determine the root cause of a defect. The ATPG tool flow is exercised in diagnostic mode, using the failing pattern syndrome to identify candidate faults. Physical locations on the die (and masks) are cross-referenced to the candidate faults for further investigation.

After wafer testing, good dies will be packaged and (likely) subjected to burn-in stress to screen infant fails. After (static or dynamic) burn-in, parts are retested. ...

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Publisher Resources

ISBN: 9780135657645