REFERENCES

1. A. R. Omondi, Computer Arithmetic Systems: Algorithms, Architecture, and Implementations. Prentice Hall International, 1994.

2. K. K. Parhi, “Fast low-power VLSI binary addition,” in Proc. of 1997 IEEE International Conference on Computer Design (ICCD), (Austin, Texas), pp. 676–68 Oct. 1997.

3. S. Waser and M. J. Flynn, Introduction to Arithmetic for Digital Systems Designers. CBS College Publishing, 1982.

4. R. P. Brent and H. T. Kung, “A regular layout for parallel adders,” IEEE Trans. on Computers, vol. C-31, no. 3, pp. 260–264, March 1982.

5. C. S. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. on Computers, vol. EC-13, pp. 14–17, Feb. 1964.

6. L. Dadda, “Some schemes for parallel multipliers,” Alta Frequenza, vol. 34, pp. 349–356, 1965.

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