(b) The adder circuit in Fig. 13.39 uses 32 transistors. Derive an optimized architecture using CMOS-transmission gates with only 24 transistors (Hint: Try to share hardware of sum and carry parts).
(c) What is the number of transistors in the critical path of an 8-bit carry-ripple adder?
Derive a truth table and logic circuit for detecting overflow for this adder using the bits x7, y7, c7, c8, and s7. (Hint: If x7 ≠ y7, i.e., the sign bits of X and Y are different, then there can never be overflow. If x7 = y7, then overflow occurs if x7 = y7 ≠ s7.)
(a) carry-save arithmetic and
(b) tree-height reduction technique,
using half and full adders and a VMA. Assume a wordlength of 8. Compute the latencies of these architectures without including the latency of the VMA.