This section addresses the design techniques used to implement asynchronous computational units using either field-programmable gate arrays (FPGAs) or full custom VLSI.

16.10.1    Full Custom VLSI Implementation

It has been shown that 2 binary handshake signals, request and acknowledge, are necessary and sufficient to realize general asynchronous networks. For efficient hardware implementation, any combinational circuit can be combined into one computational block, provided that the request and acknowledge signals can be generated along the data path. The differential cascode voltage switch logic (DCVSL) has become popular among asynchronous circuit designers because it offers an elegant way to generate the completion signals. The general structure of a DCVSL block is shown in Fig. 16.48, where the request signal can be viewed as the completion signal from the previous block. When the request line is active low, the 2 output data lines will be pulled up by the PMOS transistors, and the done signal will be pulled down. When the request line goes high, indicating that the computation of the preceding stage has been completed and that the control/data signals are stable for evaluation, the two PMOS transistors will be turned off and the input lines will be evaluated by the NMOS tree. The NMOS tree itself is designed such that only one of the output data lines (f/) will be pulled down by the NMOS tree, causing the complete signal to be ...

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