This section derives a family of systolic arrays for FIR digital filters using the linear mapping technique.
The systolic design B1 is derived by selecting the projection vector, processor vector, and scheduling vector as follows:
Using these definitions, we can show that:
Therefore, all nodes on a horizontal line are mapped to the same processor.
The block diagram of B1 systolic array design is then constructed as shown in Fig. 7.3. The low-level implementation of ...