VLSI

6 Soft-Error Mitigation Approaches for High-Performance Processor Memories

Lawrence T. Clark

Contents

6.1 Introduction

6.1.1 Static Random-Access Memory/Cache Circuits

6.1.2 Soft-Error Mechanisms

6.1.2.1 Charge Collection Physics

6.1.2.2 Circuit Cross-Section Measurements

6.1.2.3 Static Random-Access Memory Single Event Effect

6.1.3 Mitigating Single Event Upset in the Cache Hierarchy and its Impact on Latency

6.2 Radiation Hardening by Design Level 1 Cache Design

6.2.1 Cache Organization

6.2.2 Circuit Design and Operation

6.2.2.1 Circuit Design

6.2.2.2 Performance

6.2.2.3 Power Dissipation

6.2.3 Hardening Features

6.2.3.1 Cache Error Detection Circuits

6.2.3.2 Single Event Upset Error Checking in the Periphery Circuits

6.2.3.3 Error Checker ...