book

VLSI Architectures for Modern Error-Correcting Codes

Name: VLSI Architectures for Modern Error-Correcting Codes
Author: Xinmiao Zhang
ISBN: 9781351831222

by Xinmiao Zhang

December 2017

Intermediate to advanced

410 pages

11h 59m

English

CRC Press

Read now

Unlock full access

Cover Page
Half title
Title Page
Copyright page
Dedication
Contents
Preface
List of Figures
List of Tables
1 Finite field arithmetic
1.1 Definitions, properties, and element representations1.2 Finite field arithmetic1.2.1 Multiplication using basis representations1.2.1.1 Standard basis multiplier1.2.1.2 Normal basis multiplier1.2.1.3 Dual basis multiplier1.2.1.4 Multiplication in composite field1.2.2 Inversion using basis representations1.2.2.1 Inversion in original field1.2.2.2 Inversion in composite field1.3 Mapping between finite field element representations1.3.1 Mapping between standard basis and composite field representations1.3.2 Mapping between power and standard basis representations1.3.3 Mapping between standard and normal basis representations

2 VLSI architecture design fundamentals
2.1 Definitions and graph representation2.2 Pipelining and retiming2.3 Parallel processing and unfolding2.4 Folding
3 Root computations for polynomials over finite fields
3.1 Root computation for general polynomials3.2 Root computation for linearized and affine polynomials3.3 Root computation for polynomials of degree two or three
4 Reed-Solomon encoder & hard-decision and erasure decoder architectures
4.1 Reed-Solomon codes4.2 Reed-Solomon encoder architectures4.3 Hard-decision Reed-Solomon decoders4.3.1 Peterson-Gorenstein-Zier 1er algorithm4.3.2 Berlekamp-Massey algorithm4.3.3 Reformulated inversionless Berlekamp-Massey algorithm and architectures4.3.4 Syndrome, error location and magnitude computation architectures4.3.5 Pipelined decoder architecture4.4 Error-and-erasure Reed-Solomon decoders
5. Algebraic soft-decision Reed-Solomon decoder architectures
5.1 Algebraic soft-decision decoding algorithms5.2 Re-encoded algebraic soft-decision decoder5.3 Re-encoding algorithms and architectures5.3.1 Simplified re-encoding and coordinate transformation schemes5.3.2 Simplified re-encoder architectures5.4 Interpolation algorithms and architectures5.4.1 Kötter’s interpolation algorithm5.4.2 Architectures for Kötter’s interpolation5.4.2.1 Discrepancy coefficient computation architecture5.4.2.2 Polynomial updating architecture5.4.2.3 Computation scheduling for Kötter’s interpolation5.4.2.4 Discrepancy coefficient properties and interpolation complexity reduction5.4.2.5 Slow-downed interpolation architecture5.4.3 Lee-O’Sullivan interpolation algorithm and simplifications5.4.4 Architectures for Lee-O’Sullivan interpolation5.4.4.1 Initial basis construction architecture5.4.4.2 Basis conversion architecture5.4.5 Kötter’s and Lee-O’Sullivan interpolation comparisons5.5 Factorization algorithm and architectures5.5.1 Prediction-based factorization architecture5.5.2 Partial-parallel factorization architecture
6 Interpolation-based Chase and generalized minimum distance decoders
6.1 Interpolation-based Chase decoder6.1.1 Backward-forward interpolation algorithms and architectures6.1.1.1 Backward-forward interpolation6.1.1.2 Unified backward-forward interpolation6.1.1.3 Generalized backward interpolation6.1.2 Eliminated factorization6.1.3 Polynomial selection schemes6.1.3.1 Polynomial selection based on root search6.1.3.2 Polynomial selection based on evaluation value testing6.1.3.3 Reduced-complexity Chase interpolation using evaluation value testing-based polynomial selection6.1.4 Chien-search-based codeword recovery6.1.5 Systematic re-encoding6.1.6 Simplified interpolation-based Chase decoder architecture6.2 Generalized minimum distance decoder6.2.1 Kotter’s one-pass GMD decoder6.2.2 Interpolation-based one-pass GMD decoder
7 BCH encoder & decoder architectures
7.1 BCH codes7.2 BCH encoder architectures7.3 Hard-decision BCH decoders7.3.1 Peterson’s algorithm7.3.2 The Berlekamp’s algorithm and implementation architectures7.3.3 3-error-correcting BCH decoder architectures7.4 Chase BCH decoder based on Berlekamp’s algorithm7.5 Interpolation-based Chase BCH decoder architectures
8 Binary LDPC codes & decoder architectures
8.1 LDPC codes8.2 LDPC decoding algorithms8.2.1 Belief propagation algorithm8.2.2 Min-sum algorithm8.2.3 Majority-logic and bit-flipping algorithms8.2.4 Finite alphabet iterative decoding algorithm8.3 LDPC decoder architectures8.3.1 Scheduling schemes8.3.1.1 Flooding scheme8.3.1.2 Sliced message-passing scheme8.3.1.3 Row-layered decoding scheme8.3.1.4 Shuffled decoding scheme8.3.1.5 Scheduling scheme comparisons8.3.2 VLSI architectures for CNUs and VNUs8.3.2.1 CNU architectures8.3.2.2 VNU architectures8.3.2.3 Message compression8.4 Low-power LDPC decoder design
9 Non-binary LDPC decoder architectures
9.1 Non-binary LDPC codes and decoding algorithms9.1.1 Belief propagation decoding algorithms9.1.1.1 Frequency-domain decoding algorithm9.1.1.2 Log-domain decoding algorithm9.1.1.3 Mixed-domain decoding algorithm9.1.2 Extended Min-sum and Min-max algorithms9.1.3 Iterative reliability-based majority-logic decoding9.2 Min-max decoder architectures9.2.1 Forward-backward Min-max check node processing9.2.1.1 Elementary step architecture with all q messages and polynomial representation9.2.1.2 Elementary step architecture with all q messages and power representation9.2.1.3 Elementary step architecture with < q messages9.2.1.4 Scheduling of elementary steps9.2.2 Trellis-based path-construction Min-max check node processing9.2.3 Simplified Min-max check node processing9.2.4 Syndrome-based Min-max check node processing9.2.5 Basis-construction Min-max check node processing9.2.6 Variable node unit architectures9.2.7 Overall NB-LDPC decoder architectures9.3 Extended Min-sum decoder architectures9.3.1 Extended Min-sum elementary step architecture keeping q′ < ′ < q messages9.3.2 Trellis-based path-construction extended Min-sum check node processing9.4 Iterative majority-logic decoder architectures9.4.1 IHRB decoders for QCNB-LDPC codes9.4.2 IHRB decoders for cyclic NB-LDPC codes9.4.3 Enhanced IHRB decoding scheme and architectures
Bibliography
Index

Overview

This book discusses practical implementation architectures for modern error-correcting codes, providing details for every functional block as well as the overall decoder architecture. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. Many examples and case studies are included. More importantly, the advantages and drawbacks of different implementation approaches and architectures are compared. Thus, this book makes an ideal reference for system and hardware designers and graduate-level courses on VLSI design and error-correcting coding.

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
and much more.

Read now

Unlock full access

More than 5,000 organizations count on O’Reilly

O’Reilly covers everything we've got, with content to help us build a world-class technology community, upgrade the capabilities and competencies of our teams, and improve overall team performance as well as their engagement.

Julian F.

Head of Cybersecurity

I wanted to learn C and C++, but it didn't click for me until I picked up an O'Reilly book. When I went on the O’Reilly platform, I was astonished to find all the books there, plus live events and sandboxes so you could play around with the technology.

Addison B.

Field Engineer

I’ve been on the O’Reilly platform for more than eight years. I use a couple of learning platforms, but I'm on O'Reilly more than anybody else. When you're there, you start learning. I'm never disappointed.

Amir M.

Data Platform Tech Lead

I'm always learning. So when I got on to O'Reilly, I was like a kid in a candy store. There are playlists. There are answers. There's on-demand training. It's worth its weight in gold, in terms of what it allows me to do.

Mark W.

Embedded Software Engineer

Publisher Resources

ISBN: 9781482229653

Cloud Computing

Data Engineering

Data Science

AI & ML

Programming Languages

Software Architecture

IT/Ops

Security

Design

Business

Soft Skills