3D Integration for VLSI Systems

Chapter 3 WAFER BONDING TECHNIQUES

Bioh Kim, Thorsten Matthias, Viorel Dragoi, Markus Wimplinger and Paul Lindner

EV Group

3D stacked IC (3D-IC) has various potential advantages over conventional system-on-chip (SoC) or system-in-package (SiP) approaches when it comes to device performance, form factor, interconnect density, heterogeneous integration, and even manufacturing costs. The continuation of Moore’s law by conventional complementary metal oxide semiconductor (CMOS) scaling is becoming more and more challenging, requiring huge capital investments. 3D-IC with through-silicon via (TSV) interconnects provides another path towards “More Moore” and “More than Moore” with relatively smaller capital investments.

The 3D-IC approach using ...