A Practical Guide to Verilog-A: Mastering the Modeling Language for Analog Devices, Circuits, and Systems

© Slobodan Mijalković 2022

S. MijalkovićA Practical Guide to Verilog-Ahttps://doi.org/10.1007/978-1-4842-6351-8_11

11. User-Defined Functions

Slobodan Mijalković¹  

(1)

The Hague, Zuid-Holland, The Netherlands

 

Besides the predefined math functions, described in the previous chapter, Verilog-A provides also a way to define our own functions. User-defined functions could be used to encapsulate self-contained segments of the code and avoid the replication of the same or very similar code sections. Moreover, testing can be carried out on each function in isolation, rather than on the whole module. This chapter describes the two main stages in using the user-defined functions, first how to define a function and second how to invoke it in the module procedural ...