A Verilog-A procedural block could be in principle interpreted as a multivariate input-output mapping. It takes a set of parameters, variables, or expressions at the input, for producing certain results at the end of the procedural evaluation sequence. In some cases, the analytical model for such procedural evaluation could be unavailable or too time-consuming for implementation. One way to overcome this problem is to implement such critical input-output procedural mappings in Verilog-A code using lookup tables. The savings in processing time can be ...
© Slobodan Mijalković 2022
S. MijalkovićA Practical Guide to Verilog-Ahttps://doi.org/10.1007/978-1-4842-6351-8_1212. Lookup Tables
Slobodan Mijalković1
(1)
The Hague, Zuid-Holland, The Netherlands
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