Chapter 1
Design in the Energy–Delay Space
1.1 Introduction
In the past, the traditional constant-field scaling [1] has led CMOS technology to continuous improvements in the speed performances while maintaining constant power density. However, a fundamental limit of constant-field scaling manifests due to the nonscaling of subthreshold slope and the increase of gate leakage as long as the minimum feature size scales down [2, 3]. Overall, the consequent continuous increase in energy consumption has become the major concern limiting the speed performances of VLSI Integrated Circuits [4], insomuch as, even for high-speed systems, designs undergo a “power limited” regime [5].
As a consequence, it is no longer possible to focus solely on optimizing the speed of circuits regardless their energy [6]. Rather, the achievement of energy efficiency, that is, finding the circuits designs allowing us to reach the desired speed under the minimum dissipation, has become the primary target [7]. Thus, a deep understanding of the energy–delay (E–D) tradeoff and the related design issues is crucial.
In this chapter, energy and delay models of digital CMOS circuits are firstly presented (Section 1.2), since they constitute the base for any E–D-related optimization technique not fully ...
