Chapter 4
Impairment-Aware Analog Circuit Design by Reconfiguring Feedback Systems
This chapter elucidates the impairment-aware analog circuit design in a mixed-mode feedback system. By reconfiguring the interconnection among building blocks in a feedback system, the process-, temperature-, and voltage-sensitive parameters of analog circuits can be measured digitally, compensated for, and recorded digitally for performance enhancement, diagnosis, and in-field testing without the need for testing equipment or signal probing. Therefore, the analog circuit can identify its own status, learns by historical memory, and adjusts itself in response to environmental changes, which is called impairment-aware design. Also, all chips embedded with the impairment-aware design can be self-tested to screen for the failure of chips to approach zero defects per million.
First, a theorem is developed, and then circuits are practically implemented to demonstrate how the power, area, performance, and testability are enhanced and the design complexity is reduced by the impairment-aware design. The demonstrated feedback systems include charge pump PLL, all-digital PLL (ADPLL), and hybrid PLL, which are used in a wireless transmitter for use in a Global System for Mobile Communications (GSM) and a wireline transmitter for use in Serial Advanced Technology Attachment (SATA).
4.1 Introduction
The use of feedback in analog circuits is powerful because a feedback ...
