On-chip Surfing Interconnect
Consider the problem of forwarding a clock signal through a chain of buffers and long wire segments as shown in Fig. 16.1a. Such chains can be used in clock distribution networks or for clock forwarding for source-synchronous communication. Here, our focus is on source synchronous designs. A fundamental problem for such a design is jitter accumulation along the chain. Even if all of the inverters are of the same design and all of the wires are of the same length, random variations due to power-supply noise, crosstalk, temperature variation, and intrachip parameter variation add jitter at each stage, and this jitter is cumulative. Furthermore, intersymbol interference (ISI) effects (aka “drafting” ) amplify jitter . These two effects, the random walk of edge timing combined with the jitter amplification of intersymbol interference, will cause a sufficiently long buffer chain to drop clock pulses even when operating at low clock frequencies. Figure 16.1b shows the maximum length chain through which a clock signal can propagate reliably as a function of the clock period. The data in this figure is from HSPICE simulations for inverters driving long wires optimized for minimum energy delay product in the TSMC 0.18 μm process: one run was performed at each target frequency, and we noted the first stage at which pulses were missing. While ...