Temperature Monitoring Issues in Nanometer CMOS Integrated Circuits
We are currently starting to witness the end of the CMOS era. Technology scaling has accomplished outstanding integration levels, for instance Intel has announced the construction of a 14 nm foundry that should be running in 2013. But we know that this trend, which followed Moore's law almost perfectly, is expiring. Technology cannot deal any more with the complex processes required by these extremely small device sizes. And the resulting integrated circuits must face two key problems:
- Manufacturing process uncertainties. With decreasing physical device dimensions, dopant atoms have become countable and no process can implant a few atoms on the same position repeatedly. This results in very low yield and reliability figures.
- Harmful effects such as high power densities, hotspots, degradation, and wastage become exacerbated with use and time.
Due to these two reasons, designers of current integrated circuits (ICs) must be aware of all those negative effects and provide mechanisms necessary to overcome them.
One of the most worrying effects in nanometer technologies is the existence of high temperature peaks in determined locations of the circuit at a particular time. This translates into the presence of hot spots, both in space and time, which are due to growing current densities, introduction of ...