Design and Test of Robust CMOS RF and mm-Wave Radios
Advances in semiconductor technology over the last decade allowed for the implementation of high-performance RF blocks in CMOS, previously dedicated to digital circuitry, opening the doors for full system integration on a single chip, or system-on-chip (SoC), having RF, analog, and digital cores embedded together. This integration although useful suffers from a number of shortcomings.
Analog and RF circuits have low yield due to process, power supply, and temperature (PVT) variations and require several expensive silicon cycles to meet their specifications. Additionally, when combined with high yield and fast switching digital circuitry, they suffer from digital noise coupling through the substrate. For this reason, the design of RFIC blocks in platform baseband SoCs has been restricted. However, recent efforts have emerged to minimize yield loss in SoCs, which has resulted in several design techniques to handle the problems of parasitic elements and process shift. This is of prime importance to the industry as it translates to reduced engineering costs, faster product development, and faster time to market.
To decrease the effect of variability on yield loss, some form of calibration for RF blocks after fabrication is needed to compensate for the loss of performance. However, calibration of these ...