Advanced Frequency Synthesis by Phase Lock

CHAPTER 9

ALL-DIGITAL FREQUENCY SYNTHESIZERS

Driven by the advantages of incorporating frequency synthesizers in ICs that are designed for digital circuits, especially those using processes that are not very compatible with analog circuitry, researchers have developed two new architectures that we will discuss here. The Flying Adder is used to generate a desired average frequency, which is not spectrally pure, while the all-digital phase-locked loop (ADPLL) synthesizer attempts to generate a spectrally pure signal.

Great importance is placed on minimizing the use of analog circuitry because it is not easily integrated into modern ICs that are designed for very high digital circuit density (e.g., deep submicron CMOS). Not only do the analog components tend to use relatively large areas but also the voltages used in these circuits are inappropriately low for analog functions, bringing them close to junction voltages and noise levels. Unfortunately, the availability of only discrete timing instances for signal transitions in clocked digital circuits presents a problem for frequency synthesizers.

A common compromise is the synthesis of signals with the desired average frequency, even though transitions deviate from the desired instants by some limited amount. We see this in the fractional-N divider, which presents an average frequency to the phase detector, but there the filtering action of the PLL, aided by cancellation from a DAC or by ΣΔ modulation, reduces the effect, at f_{out ...}