Advanced Frequency Synthesis by Phase Lock

APPENDIX A

ALL DIGITAL

A.1   FLYING ADDER CIRCUITS

Mair and Xiu [2000] show versions of the Flying Adder that provide for controllable phase delay and for higher speed operation. A version of the latter circuit [Xiu and You, 2002] is shown in Fig. A.1. The objective here is not only to increase maximum output frequency but also to avoid a potential problem when addresses to the mux change, at which time some intermediate state may occur during switching and erroneously trigger the output bistable. However, it would seem that the output flip-flop could be made to ignore these glitches if an appropriate delay were inserted into the feedback from output to D input (Fig. A.2) or possibly by other logic design methods.

In Fig. A.1, the input to the top register receives the sum of the MSBs from the accumulator and [K/2], that is the (m − 1) MSBs from k, shifted down 1 bit. They will select a phase that is midway between outputs from the lower mux, if K is even, otherwise a little less. The switch S_out selects the two muxes alternately, so each outputs from the lower mux will be followed by a delayed output from the upper mux. As a result, the signal at f_x will be square (if K is even) and can provide a uniform pulse at frequency f_x. The mux to which flip-flop FF is connected will not receive an address change while it is connected. When a positive edge drives FF, the mux will be switched, but S_out will connect FF to the other mux at that time. An extra register has been inserted into ...