REFERENCES

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Arora, H., Klemmer, N., Morizio, J., and Wolf, P. (2005). “Enhanced phase noise modeling of fractional-N frequency synthesizers. ” IEEE Transactions on Circuits and Systems I: Regular Papers 52(2) (February), 379–395.

Banerjee, D. (2006). PLL Performance, Simulation, and Design, 4th ed. Dog Ear Publishing, LLC. Available at http://www.national.com/analog/timing/pll_designbook. See also Banerjee [2008].

Banerjee, D. (2008). “Fractional N frequency synthesis.” National Semiconductor Application Note 1879, Santa Clara, CA: National Semiconductor, December 10.

Bizjak, L., Da Dalt, N., Thurner, P., Nonis, R., Palestri, P., and Selmi L. (2008). “Comprehensive behavioral modeling of conventional and dual-tuning PLLs.” IEEE Transactions on Circuits and Systems I: Regular Papers 55(6) (July), 1628–1638.

Boon, C. C., Do, M. A., Yeo, K. S., and Ma, J. G. (2005). “Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction.” IEEE Transactions on Circuits and Systems I: Regular Papers 52(6) (June), 1042–1048.

Borkowski, M., Riley, T., Häkkinen, J., and Kostamovaara, J. (2005). “A practical Δ−Σ modulator design method based on periodical behavior analysis.” IEEE Transactions on Circuits and Systems II: Express Briefs 52(10) (October), 626–630.

Bracewell, R. (1965). The Fourier Transform ...

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