11.1 I/O Design Considerations

11.2 Push-Pull Transmitters

11.2.1 Operation

11.2.2 Linear Models

11.2.3 Nonlinear models

11.2.4 Advanced Design Considerations

11.3 CMOS receivers

11.3.1 Operation

11.3.2 Modeling

11.3.3 Advanced design considerations

11.4 ESD Protection Circuits

11.4.1 Operation

11.4.2 Modeling

11.4.3 Advanced design considerations

11.5 On-Chip Termination

11.5.1 Operation

11.5.2 Modeling

11.5.3 Advanced design considerations

11.6 Bergeron Diagrams

11.6.1 Theory and method

11.6.2 Limitations

11.7 Open-Drain Transmitters

11.7.1 Operation

11.7.2 Modeling

11.7.3 Advanced Design Considerations

11.8 Differential Current-Mode Transmitters

11.8.1 Operation

11.8.2 Advanced Design Considerations

11.9 Low-Swing and Differential Receivers

11.9.1 Operation

11.9.2 Modeling

11.9.3 Advanced Design Considerations

11.10 IBIS Models

11.10.1 Model Structure and Development Process

11.10.2 Generating Model Data

11.10.3 Differential I/O Models

11.10.4 Example of an IBIS File

11.11 Summary



So far we have discussed the behavior of high-speed interconnects and have provided techniques for analyzing and modeling the key physical phenomena that affect signal quality at multi-Gb/s data rates. To fully analyze and understand the behavior of high-speed signaling links, we must include the I/O circuits that transmit and receive the digital data. Design of high-performance links demands that the circuits and interconnects be jointly optimized as ...

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