12
EQUALIZATION
12.1 Analysis and Design Background
12.1.1 Maximum Data Transfer Capacity
12.1.2 Linear Time–Invariant Systems
12.1.3 Ideal Versus Practical Interconnects
12.1.4 Equalization Overview
12.2 Continuous-Time Linear Equalizers
12.2.1 Passive CTLEs
12.2.2 Active CTLEs
12.3 Discrete Linear Equalizers
12.3.1 Transmitter Equalization
12.3.2 Coefficient Selection
12.3.3 Receiver Equalization
12.3.4 Nonidealities in DLEs
12.3.5 Adaptive Equalization
12.4 Decision Feedback Equalization
12.5 Summary
References
Problems
We have already discussed the impact of Moore’s law, which drives the interchip data bandwidth to continually increasing performance levels. We have also shown that nonideal aspects of transmission lines, such as crosstalk and losses, can have a significant impact on signal integrity and timing. These impacts dominate at multi–Gb/s speeds, causing “smearing” of signals so that their energy is spread over multiple bit positions, a phenomenon known as intersymbol interference (ISI). The impact of ISI is an increase in the jitter that degrades the timing margin and a distortion in the signal levels that degrades the voltage margin of the interchip signaling link. Equalization is a circuit technique that reduces the ISI–induced timing jitter and voltage margin loss by compensating for nonideal aspects, in particular the loss of interconnects at high speed.
In this chapter we adopt a communications channel–based approach to analyz–ing our signaling interfaces. Communications ...
