Interleaving of Successive-Approximation Register ADCs in Deep Sub-Micron CMOS Technology
Kostas Doris, Erwin Janssen, Yu Lin, Athon Zanikopoulos and Alessandro Murroni, NXP Semiconductors, High Tech Campus HTC32, 5656AE Eindhoven, The Netherlands
Introduction
The Successive-Approximation-Register ADC (SAR) architecture receives major attention nowadays because it adapts itself optimally to its deep sub-micron CMOS silicon medium, favoring its simplicity. Its most popular implementation, shown in Figure 10.1, consists of merely a comparator, logic, and a capacitor DAC [1] that approximates serially the input signal. SARs are considered slow converters due to their sequential algorithmic operation, but they cover up this weakness, ...
Get Advances in Analog and RF IC Design for Wireless Communication Systems now with the O’Reilly learning platform.
O’Reilly members experience books, live events, courses curated by job role, and more from O’Reilly and nearly 200 top publishers.
