Interleaving of Successive-Approximation Register ADCs in Deep Sub-Micron CMOS Technology
Kostas Doris, Erwin Janssen, Yu Lin, Athon Zanikopoulos and Alessandro Murroni, NXP Semiconductors, High Tech Campus HTC32, 5656AE Eindhoven, The Netherlands
The Successive-Approximation-Register ADC (SAR) architecture receives major attention nowadays because it adapts itself optimally to its deep sub-micron CMOS silicon medium, favoring its simplicity. Its most popular implementation, shown in Figure 10.1, consists of merely a comparator, logic, and a capacitor DAC  that approximates serially the input signal. SARs are considered slow converters due to their sequential algorithmic operation, but they cover up this weakness, ...