Book description
Examines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges
Embedded and fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons.
Filled with contributions from some of the field's leading experts,Advances in Embedded and Fan-Out Wafer Level Packaging Technologies begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions.
- Discusses specific company standards and their development results
- Content relates to practice as well as to contemporary and future challenges in electronics system integration and packaging
Advances in Embedded and Fan-Out Wafer Level Packaging Technologies will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research.
Table of contents
- Cover
- Preface
- List of Contributors
- Acknowledgments
-
1 History of Embedded and Fan‐Out Packaging Technology
- 1.1 Introduction
- 1.2 First Embedding Technologies Based on MCM‐D Concepts
- 1.3 First Embedding Technologies Based on Organic Laminates and Flex
- 1.4 Helsinki University of Technology and Imbera Electronics Embedded Chips
- 1.5 Fraunhofer IZM/TU Berlin Chip‐in‐Polymer (CiP)
- 1.6 HiCoFlex, Chip‐in‐Flex, and UTCP
- 1.7 Conclusion
- References
- 2 FO‐WLP Market and Technology Trends
-
3 Embedded Wafer‐Level Ball Grid Array (eWLB) Packaging Technology Platform
- 3.1 Technology Description
- 3.2 Basic Package Construction
- 3.3 Manufacturing Process Flow and BOM
- 3.4 System Integration Capability
- 3.5 Manufacturing Format and Scalability
- 3.6 Package Performance
- 3.7 Robustness and Reliability Data
- 3.8 Electrical Test Considerations
- 3.9 Applications and Markets
- References
- 4 Ultrathin 3D FO‐WLP eWLB‐PoP (Embedded Wafer‐Level Ball Grid Array‐Package‐on‐Package) Technology
- 5 NEPES’ Fan‐Out Packaging Technology from Single die, SiP to Panel‐Level Packaging
-
6 M‐Series™ Fan‐Out with Adaptive Patterning™
- 6.1 Technology Description
- 6.2 Basic Package Construction
- 6.3 Manufacturing Process Flow and BOM
- 6.4 Design Features and System Integration Capability
- 6.5 Adaptive Patterning
- 6.6 Manufacturing Format and Scalability
- 6.7 Robustness and Reliability Data
- 6.8 Electrical Test Considerations
- 6.9 Applications and Markets
- Acknowledgment
- References
- 7 SWIFT® Semiconductor Packaging Technology
- 8 Embedded Silicon Fan‐Out (eSiFO®) Technology for Wafer‐Level System Integration
-
9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology
- 9.1 Technology Description
- 9.2 Basic Interposer Construction
- 9.3 Manufacturing Process Flow and BOM
- 9.4 Design Features
- 9.5 System Integration Capability
- 9.6 Manufacturing Format and Scalability
- 9.7 Package Performance
- 9.8 Robustness and Reliability Data
- 9.9 Electrical Test Considerations
- 9.10 Applications and Markets
- 9.11 Summary
- References
- 10 Embedding of Power Electronic Components: The Smart p2 Pack Technology
-
11 Embedded Die in Substrate (Panel‐Level) Packaging Technology
- 11.1 Technology Description
- 11.2 Basic Package Construction
- 11.3 Manufacturing Process Flow and BOM
- 11.4 Design Features
- 11.5 System Integration Capability
- 11.6 Package Performance
- 11.7 Diversity of EDS Technology: Module
- 11.8 Diversity of EDS Technology: Power Devices
- 11.9 Applications and Markets
- References
-
12 Blade: A Chip‐First Embedded Technology for Power Packaging
- 12.1 Technology Description
- 12.2 Development and Implementation
- 12.3 Basic Package Construction
- 12.4 Manufacturing Process Flow and BOM
- 12.5 Design Features
- 12.6 System Integration Capability
- 12.7 Manufacturing Format and Scalability
- 12.8 Package Performance
- 12.9 Robustness and Reliability Data
- 12.10 Electrical Test Considerations
- 12.11 Applications and Markets
- Acknowledgments
- References
-
13 The Role of Liquid Molding Compounds in the Success of Fan‐Out Wafer‐Level Packaging Technology
- 13.1 Introduction
- 13.2 The Necessity of Liquid Molding Compound for FO‐WLP
- 13.3 The Required Parameters of Liquid Molding Compound for FO‐WLP
- 13.4 Design of LMC Resin Formulation
- 13.5 Development of LMC in Connection with Latest Requirements
- 13.6 Current LMC Representative Proprieties
- 13.7 Conclusions
- Acknowledgment
- References
-
14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan‐Out Wafer‐Level Packaging (FO‐WLP)
- 14.1 Introduction
- 14.2 Brief History of PI/PBO‐Based Materials in Semiconductor Applications
- 14.3 Dielectric Challenges in FO‐WLP Applications
- 14.4 HDM Material Sets for FO‐WLP
- 14.5 PBO‐Gen3 (Positive‐Acting, Aqueous‐Developable Material)
- 14.6 PBO‐Gen3 Process Flow
- 14.7 PBO‐Gen3 Lithography
- 14.8 PBO‐Gen3 Material Properties
- 14.9 PBO‐Gen3 Dielectric Reliability Testing
- 14.10 PBO‐Gen3 Package Reliability Performance (TCT Testing at Component and Board Level)
- 14.11 Performance Comparison Between PBO‐Gen3 and PBO‐Gen2
- 14.12 PI‐Gen2 (Negative‐Acting, Solvent‐Developable Material)
- 14.13 PI‐Gen2 Process Flow
- 14.14 PI‐Gen2 Lithography
- 14.15 PI‐Gen2 Material Properties
- 14.16 PI‐Gen2 Dielectric Reliability Data
- 14.17 PI‐Gen2 Package Reliability Performance (Component and Board Level)
- 14.18 Comparison Between PBO‐Gen3 and PI‐Gen2
- 14.19 Summary
- References
- 15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer‐Level Packaging
-
16 The Role of Pick and Place in Fan‐Out Wafer‐Level Packaging
- 16.1 Introduction
- 16.2 Equipment Requirements for Fan‐Out Bonders
- 16.3 Avoiding Fan‐Out Bonding Pitfalls
- 16.4 Equipment Qualification for Fan‐Out Pick and Place
- 16.5 Running a Large Area Glass‐on‐Glass Process
- 16.6 Running a Glass‐on‐Carrier Process
- 16.7 Running a Reference Production Lot with Test Die
- 16.8 Conclusions
- References
-
17 Process and Equipment for eWLB: Chip Embedding by Molding
- 17.1 Introduction
- 17.2 Historical Background Molding
- 17.3 The Molded Wafer Idea: Key for the Fan‐Out eWLB Technology
- 17.4 The Compression Molding Process
- 17.5 Principle Challenges for Chip Embedding with Compression Molding
- 17.6 Process Development Solutions for Principle Challenges
- 17.7 Compression Molding Equipment for Chip Embedding
- 17.8 Chip Embedding Features Achieved by Compression Molding
- 17.9 Conclusions and Next Steps
- Acknowledgments
- References
- 18 Tools for Fan‐Out Wafer‐Level Package Processing
- 19 Equipment and Process for eWLB: Required PVD/Sputter Solutions
- 20 Excimer Laser Ablation for the Patterning of Ultra‐fine Routings
- 21 Temporary Carrier Technologies for eWLB and RDL‐First Fan‐Out Wafer‐Level Packages
- 22 Encapsulated Wafer‐Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection
- 23 Embedded Multi‐die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect
- 24 Interconnection Technology Innovations in2.5D Integrated Electronic Systems
- Index
- End User License Agreement
Product information
- Title: Advances in Embedded and Fan-Out Wafer Level Packaging Technologies
- Author(s):
- Release date: February 2019
- Publisher(s): Wiley-IEEE Press
- ISBN: 9781119314134
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