Advances in Embedded and Fan-Out Wafer Level Packaging Technologies

18Tools for Fan‐Out Wafer‐Level Package Processing

Nelson Fan, Eric Kuah, Eric Ng, and Otto Cheung

ASM Pacific Technology

18.1 Turnkey Solution for Fan‐Out Wafer‐Level Packaging

In this chapter, we discuss three critical processes for fan‐out wafer‐level packaging (FO‐WLP) technology. They are die placement, large format encapsulation, and handling of finished packages after singulation. Unlike traditional packaging platforms, the majority of FO‐WLP is being manufactured in 12 in. wafer formats rather than small strip formats. Moreover, the FO‐WLP technology platform is flexible as it can address different device design requirements with densely routed redistribution layers (RDL) and by deploying many different die placement approaches, such as chip‐first and chip‐last coupling with either a local or global alignment method. Depending on which approach is being used, the die placement can be done at room temperature or at an elevated temperature with die facing up or facing down. During molding, the reconstructed wafer can also be molded with either die face‐up or face‐down orientation, depending on the package structure. Specifically, the latter is deployed for process designs comprising molded underfill (MUF) processes. Often, packaging subcontract manufacturers offer multiple fan‐out approaches to their customers; therefore, the required die placement tool and encapsulation tool both have to be able to handle large format material and be flexible and robust enough to ...