The need for heterogeneous network-on-chip architectures with GPGPUs
A case study with photonic interconnects
N. Mansoor; A. Ganguly; S.L. Alarcon Rochester Institute of Technology, Rochester, NY, United States
Abstract
Future multicore chips will have hundreds of heterogeneous components including processing engines, custom logic, GPU units, programmable fabrics, and distributed memory. Such multicore chips are expected to run varied multiple parallel workloads simultaneously. Hence different communicating cores will require different bandwidths leading to the necessity of a heterogeneous network-on-chip (NoC) architecture. Simply over-provisioning for performance will invariably result in loss of power efficiency. Moreover, ...
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