Architecting the last-level cache for GPUs using STT-MRAM nonvolatile memory
M.H. Samavatian1; M. Arjomand1; R. Bashizade1; H. Sarbazi-Azad1,2 1 Sharif University of Technology, Tehran, Iran2 Institute for Research in Fundamental Sciences (IPM), Tehran, Iran
Abstract
The key to high performance on graphics processor units (GPUs) is the massive threading that helps GPUs hide memory access latency with maximum thread-level parallelism (TLP). Although, increasing the TLP and the number of cores does not result in enhanced performance because of thread contention for memory resources such as last-level cache. The future GPUs will have larger last-level cache (L2 in GPU), based on the current trends in VLSI technology and GPU architectures ...
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