Multi-bit NAND Flash memories for ultra high density storage devices

R. Micheloni and L. Crippa,    PMC-Sierra, Italy


This chapter is about NAND Flash memories, which have outpaced DRAMs in the technology scaling race. The first part of this work is devoted to the basics of this technology, including array architectures and operations (read, program and erase). Multi-bit per cell approaches (MLC and TLC) are also described, because they strongly drive the price reduction at the cost of reduced reliability. Lastly, the new 3D approach is introduced: the industry is still in a development phase, and here we present a summary of the pros and cons of the most promising candidates.

Key words

NAND Flash; MLC; TLC; charge trap; 3D array

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