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All-Digital Frequency Synthesizer in Deep-Submicron CMOS by Poras T. Balsara, Robert B. Staszewski

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PREFACE

Design flow and circuit techniques of contemporary transceivers for multigigahertz mobile radio-frequency (RF) wireless applications are typically quite analog intensive and utilize process technologies that are incompatible with a digital baseband (DBB) and application processor (AP). Nowadays, the DBB and AP designs constantly migrate to the most advanced deep-submicron digital CMOS process available, which usually does not offer any analog extensions and has very limited voltage headroom. The aggressive cost and power reductions of high-volume mobile wireless solutions can realistically only be achieved by the highest level of integration, and this favors a digitally intensive approach to conventional radio-frequency (RF) functions in the most advanced deep-submicron process.

Given the task of designing highly integrated RF circuits in the digital deep-submicron process environment, we have realized that we are facing a new paradigm: In a deep-submicron CMOS process, time-domain resolution of a digital signal edge transition is superior to voltage resolution of analog signals. This is in clear contrast with the older process technologies, which rely on a high supply voltage (originally, 15 V, then 5 V, and finally, 3.3 and 2.5 V) and a stand-alone configuration with few extraneous noise sources in order to achieve a good signal-to-noise ratio and resolution in the voltage domain, often at the cost of a long settling time. In a deep-submicron process, with its low supply ...

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