All-Digital Frequency Synthesizer in Deep-Submicron CMOS

CHAPTER 6

BEHAVIORAL MODELING AND SIMULATION

With the first demonstration of a fully digital frequency synthesizer and transmitter for wireless applications, a need has arisen to model and simulate RF components using the same simulation engine as that used for the digital back end, which at present is likely to contain over a million gates. In this way, complex interactions and performance of an entire system-on-chip (SoC) integrated circuit (IC) could be validated and verified prior to tape-out. Here are some examples of these complex interactions:

1. Effect of the TDC resolution and nonlinearity on the close-in PLL phase noise performance and generated spurs
2. Effect of the DCO phase noise on PLL phase noise performance and spurs generated, especially when the PLL contains a higher-order digital loop filter and operates in fractional-N mode
3. Effect of the DCO frequency resolution on the close-in phase noise of a PLL
4. Effect of the ΣΔ DCO dithering on the far-out phase noise
5. Effect of the DCO varactor mismatches on the modulated spectrum
6. Effect of the DPA resolution and nonlinearity on the RF output spectrum

Although SPICE-based simulation tools are extremely useful for small RF circuits containing several components (such as an RF oscillator), their slow simulation performance prevents us from investigating larger circuits (such as an RF oscillator with a PLL and a transmitter or receiver). In fact, using the techniques presented, we were able to determine that the entire transmitter ...