Analog MOS Integrated Circuits for Signal Processing

INDEX

Acceptors, 65

ADC:

flash, 425

successive approximation, 420–425

Aliasing, 39

Amplitude modulators, see Modulators

Analog antialiasing filter (AAF), 530–532

Analog-to-digital converter, see ADC

Antialiasing, 530–539

Autozeroing, 422

Band-gap reference voltage, 558–559

Bilinear ladder filter design, 318–339

Bilinear s-to-z transformation, 50–51, 276

design using it, 51–55

Binary weighted capacitor arrays, see Programmable capacitor arrays (PCA)

Biquad:

high-Q, 287–296

low-Q, 281–287

Bode plot, 174

Body effect, 77–78

Boot-strapped clock driver, 463–464

Built-in voltage, 68

Capacitance spread, 284

Capacitors, 86–93

Channel, 70

channel-length modulation, 73

Chopper-stabilized amplifier, 502–503

Clock, 1

feedthrough, 94–95

frequency, 7

period, 4

signal, 94, 95

C-message noise weighting, 560

CMOS amplifiers, 168–189, 246–259

process, 111–112, 115–116

Common centroid geometry, 476–479

Common-mode rejection ratio (CMRR), 122, 211

Companding:

A-law, 551–552

definition, 549

μ-law, 551–552

Comparators, 422–423, 425–437

autozeroed, 422–423, 431

differential, 431–432

Composite load, 139

Convolution, 23

Correlated double samplings (CDS), 502

Cosine filter, 537, 554

Current source, 128–133

cascode, 131

improved MOS Wilson's, 131

Wilson's, 129

DAC, 420

Data modems, 561–564

Decimator, 533–539

implementation of, 534–539

response of, 533–534

Depletion–mode MOSFET, 76

Depletion region, 68

Deposition, 102–103

Design example:

bilinear ladder design, 355–360

cascode design, 350–355

LDI ladder design, ...