Architecting and Building High-Speed SoCs

Architecting and Building High-Speed SoCs

by Mounir Maaref
Released December 2022
Publisher(s): Packt Publishing
ISBN: 9781801810999

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Book description

Design a high-speed SoC while gaining a holistic view of the FPGA design flow and overcoming its challenges.

Purchase of the print or kindle book includes a free eBook in the PDF format.

Key Features

  • Use development tools to implement and verify an SoC, including ARM CPUs and the FPGA logic
  • Overcome the challenge of time to market by using FPGA SoCs and avoid the prohibitive ASIC NRE cost
  • Understand the integration of custom logic accelerators and the SoC software and build them

Book Description

Modern and complex SoCs can adapt to many demanding system requirements by combining the processing power of ARM processors and the feature-rich Xilinx FPGAs. You'll need to understand many protocols, use a variety of internal and external interfaces, pinpoint the bottlenecks, and define the architecture of an SoC in an FPGA to produce a superior solution in a timely and cost-efficient manner.

This book adopts a practical approach to helping you master both the hardware and software design flows, understand key interconnects and interfaces, analyze the system performance and enhance it using the acceleration techniques, and finally build an RTOS-based software application for an advanced SoC design.

You'll start with an introduction to the FPGA SoCs technology fundamentals and their associated development design tools. Gradually, the book will guide you through building the SoC hardware and software, starting from the architecture definition to testing on a demo board or a virtual platform. The level of complexity evolves as the book progresses and covers advanced applications such as communications, security, and coherent hardware acceleration.

By the end of this book, you'll have learned the concepts underlying FPGA SoCs' advanced features and you'll have constructed a high-speed SoC targeting a high-end FPGA from the ground up.

What you will learn

  • Understand SoC FPGAs' main features, advanced buses and interface protocols
  • Develop and verify an SoC hardware platform targeting an FPGA-based SoC
  • Explore and use the main tools for building the SoC hardware and software
  • Build advanced SoCs using hardware acceleration with custom IPs
  • Implement an OS-based software application targeting an FPGA-based SoC
  • Understand the hardware and software integration techniques for SoC FPGAs
  • Use tools to co-debug the SoC software and hardware
  • Gain insights into communication and DSP principles in FPGA-based SoCs

Who this book is for

This book is for FPGA and ASIC hardware and firmware developers, IoT engineers, SoC architects, and anyone interested in understanding the process of developing a complex SoC, including all aspects of the hardware design and the associated firmware design. Prior knowledge of digital electronics, and some experience of coding in VHDL or Verilog and C or a similar language suitable for embedded systems will be required for using this book. A general understanding of FPGA and CPU architecture will also be helpful but not mandatory.

Table of contents

  1. Architecting and Building High-Speed SoCs
  2. Contributors
  3. About the author
  4. About the reviewer
  5. Preface
    1. Who this book is for
    2. What this book covers
    3. To get the most out of this book
    4. Download the example code files
    5. Code in Action
    6. Download the color images
    7. Conventions used
    8. Get in touch
    9. Share Your Thoughts
    10. Download a free PDF copy of this book
  6. Part 1: Fundamentals and the Main Features of High-Speed SoC and FPGA Designs
  7. Chapter 1: Introducing FPGA Devices and SoCs
    1. Xilinx FPGA devices overview
      1. A brief historical overview
      2. FPGA devices and penetrated vertical markets
      3. An overview of the Xilinx FPGA device families
      4. An overview of the Xilinx FPGA devices features
    2. Xilinx SoC overview and history
      1. A short survey of the Xilinx SoC FPGAs based on an ARM CPU
    3. Xilinx Zynq-7000 SoC family hardware features
      1. Zynq-7000 SoC APU
      2. Zynq-7000 SoC memory controllers
      3. Zynq-7000 I/O peripherals block
      4. Zynq-7000 SoC interconnect
    4. Xilinx Zynq Ultrascale+ MPSoC family overview
      1. Zynq UltraScale+ MPSoC APU
      2. Zynq UltraScale+ MPSoC RPU
      3. Zynq UltraScale+ MPSoC GPU
      4. Zynq UltraScale+ MPSoC VCU
      5. Zynq UltraScale+ MPSoC PMU
      6. Zynq UltraScale+ MPSoC DMA channels
      7. Zynq UltraScale+ MPSoC memory interfaces
      8. Zynq-UltraScale+ MPSoC IOs
      9. Zynq UltraScale+ MPSoC IOP block
      10. Zynq-UltraScale+ MPSoC interconnect
    5. SoC in ASIC technologies
      1. High-level design steps of an SoC in an ASIC
    6. Summary
    7. Questions
  8. Chapter 2: FPGA Devices and SoC Design Tools
    1. Technical requirements
    2. FPGA hardware design flow and tools overview
      1. FPGA hardware design flow
      2. FPGA hardware design tools
    3. FPGA SoC hardware design tools
      1. Using the Vivado IP Integrator to create a sample SoC hardware
    4. FPGA and SoC hardware verification flow and associated tools
      1. Adding the cross-triggering debug capability to the FPGA SoC design
    5. FPGA SoC software design flow and associated tools
      1. Vitis IDE embedded software design flow overview
      2. Vitis IDE embedded software design terminology
      3. Vitis IDE embedded software design steps
    6. Summary
    7. Questions
  9. Chapter 3: Basic and Advanced On-Chip Busses and Interconnects
    1. On-chip buses and interconnects overview
      1. On-chip bus overview
      2. On-chip interconnects
    2. ARM AMBA interconnect protocols suite
      1. ARM AMBA standard historical overview
      2. APB bus protocol overview
      3. AXI bus protocol overview
      4. AXI Stream bus protocol overview
      5. ACE bus protocol overview
    3. OCP interconnect protocol
      1. OCP protocol overview
      2. OCP bus characteristics
      3. OCP bus interface signals
      4. OCP bus-supported transactions
    4. DMA engines and data movements
      1. IP-integrated DMA engines overview
      2. IP-integrated DMA engines topology and operations
      3. Standalone DMA engines overview
      4. Central DMA engines topology and operations
    5. Data sharing and coherency challenges
      1. Data access atomicity
      2. Cache coherency overview
    6. Summary
    7. Questions
  10. Chapter 4: Connecting High-Speed Devices Using Buses and Interconnects
    1. Legacy off-chip interconnects overview
      1. SPI overview
      2. Zynq-7000 SoC SPI controller overview
      3. I2C overview
      4. Zynq-7000 SoC I2C controller overview
    2. Introduction to the PCIe interconnect
      1. Historical overview of the PCIe interconnect
      2. PCIe interconnect system topologies
      3. PCIe protocol layers
      4. PCIe controller example
      5. PCIe subsystem data exchange protocol example using DMA
      6. PCIe system performance considerations
    3. Ethernet interconnect
      1. Ethernet speeds historical evolution
      2. Ethernet protocol overview
      3. Ethernet interface of the Zynq-7000 SoC overview
    4. Introduction to the Gen-Z protocol
      1. Gen-Z protocol architectural features
      2. SoC design and Gen-Z fabric
    5. CCIX protocol and off-chip data coherency
      1. CCIX protocol architectural features
    6. Summary
    7. Questions
  11. Chapter 5: Basic and Advanced SoC Interfaces
    1. Interface definition by function
      1. SoC interface characteristics
      2. SoC interface quantitative considerations
    2. Processor cache fundamentals
      1. Processor cache organization
    3. Processor MMU fundamentals
    4. Memory and storage interface topology
      1. DDR memory controller
      2. Static memory controller
      3. On-chip memory controller
    5. Summary
    6. Questions
  12. Part 2: Implementing High-Speed SoC Designs in an FPGA
  13. Chapter 6: What Goes Where in a High-Speed SoC Design
    1. The SoC architecture exploration phase
      1. SoCs PS processors block features
      2. Memory and storage interfaces
      3. Communication interfaces
      4. PS block dedicated hardware functions
      5. FPGA SoC device general characteristics
    2. SoC hardware and software partitioning
      1. A simple SoC example – an electronic trading system
    3. Hardware and software interfacing and communication
      1. Data path models of the ETS
    4. Introducing the Semi-Soft algorithm
      1. Using the Semi-Soft algorithm approach in the Zynq-based SoCs
      2. Using system-level alternative solutions
      3. Introduction to OpenCL
      4. Exploring FPGA partial reconfiguration as an alternative method
    5. Early SoC architecture modeling and the golden model
      1. System modeling using Accellera SystemC and TLM2.0
      2. System modeling using Synopsys Platform Architect
      3. System modeling using the gem5 framework
      4. System modeling using the QEMU framework and SystemC/TLM2.0
    6. Summary
    7. Questions
  14. Chapter 7: FPGA SoC Hardware Design and Verification Flow
    1. Technical requirements
    2. Installing the Vivado tools on a Linux VM
      1. Installing Oracle VirtualBox and the Ubuntu Linux VM
      2. Installing Vivado on the Ubuntu Linux VM
    3. Developing the SoC hardware microarchitecture
      1. The ETS SoC hardware microarchitecture
    4. Design capture of an FPGA SoC hardware subsystem
      1. Creating the Vivado project for the ETS SoC
      2. Configuring the PS block for the ETS SoC
      3. Adding and configuring the required IPs in the PL block for the ETS SoC
    5. Understanding the design constraints and PPA
      1. What is the PPA?
      2. Synthesis tool parameters affecting the PPA
      3. Specifying the synthesis options for the ETS SoC design
      4. Implementation tool parameters affecting the PPA
      5. Specifying the implementation options for the ETS SoC design
      6. Specifying the implementation constraints for the ETS SoC design
      7. SoC hardware subsystem integration into the FPGA top-level design
    6. Verifying the FPGA SoC design using RTL simulation
      1. Customizing the ETS SoC design verification test bench
      2. Hardware verification of the ETS SoC design using the test bench
    7. Implementing the FPGA SoC design and FPGA hardware image generation
      1. ETS SoC design implementation
      2. ETS SoC design FPGA bitstream generation
    8. Summary
    9. Questions
  15. Chapter 8: FPGA SoC Software Design Flow
    1. Technical requirements
    2. Major steps of the SoC software design flow
      1. ETS SoC XSA archive file generation in the Vivado IDE
      2. ETS SoC software project setup in Vitis IDE
      3. ETS SoC MicroBlaze software project setup in the Vitis IDE
      4. ETS SoC PS Cortex-A9 software project setup in the Vitis IDE
    3. Setting up the BSP, boot software, drivers, and libraries for the software project
      1. Setting up the BSP for the ETS SoC MicroBlaze PP application project
      2. Setting up the BSP for the ETS SoC Cortex-A9 core0 application project
      3. Setting up the BSP for the ETS SoC boot application project
    4. Defining the distributed software microarchitecture for the ETS SoC processors
      1. A simplified view of the ETS SoC hardware microarchitecture
      2. A summary of the data exchange mechanisms for the ETS SoC Cortex-A9 and the MicroBlaze IPC
      3. The ETMP protocol overview
      4. The ETS SoC system address map
      5. The Ethernet MAC and its DMA engine software control mechanisms
      6. The AXI INTC software control mechanisms
      7. Quantitative analysis and system performance estimation
      8. The ETS SoC Cortex-A9 software microarchitecture
      9. The ETS SoC MicroBlaze PP software microarchitecture
    5. Building the user software applications to initialize and test the SoC hardware
      1. Specifying the linker script for the ETS SoC projects
      2. Setting the compilation options and building the executable file for the Cortex-A9
    6. Summary
    7. Questions
  16. Chapter 9: SoC Design Hardware and Software Integration
    1. Technical requirements
    2. Connecting to an FPGA SoC board and configuring the FPGA
    3. The emulation platform for running the embedded software
    4. Using QEMU in the Vitis IDE with the ETS SoC project
    5. Using the emulation platform for debugging the SoC test software
    6. Embedded software profiling using the Vitis IDE
    7. Summary
    8. Questions
  17. Part 3: Implementation and Integration of Advanced High-Speed FPGA SoCs
  18. Chapter 10: Building a Complex SoC Hardware Targeting an FPGA
    1. Technical requirements
    2. Building a complex SoC subsystem using Vivado IDE
    3. System performance analysis and the system quantitative studies
    4. Addressing the system coherency and using the Cortex-A9 ACP port
      1. Overview of the Cortex-A9 CPU ACP in the Zynq-7000 SoC FPGA
      2. Implications of using the ACP interface in the ETS SoC design
    5. Summary
    6. Questions
  19. Chapter 11: Addressing the Security Aspects of an FPGA-Based SoC
    1. FPGA SoC hardware security features
    2. ARM CPUs and their hardware security paradigm
      1. ARM TrustZone hardware features
    3. Software security aspects and how they integrate the hardware’s available features
    4. Building a secure FPGA-based SoC
    5. Summary
    6. Questions
  20. Chapter 12: Building a Complex Software with an Embedded Operating System Flow
    1. Technical requirements
    2. Embedded OS software design flow for Xilinx FPGA-based SoCs
    3. Customizing and generating the BSP and the bootloader for FreeRTOS
    4. Building a user application and running it on the target
    5. Summary
    6. Questions
  21. Chapter 13: Video, Image, and DSP Processing Principles in an FPGA and SoCs
    1. DSP techniques using FPGAs
      1. Zynq-7000 SoC FPGA Cortex-A9 processor cluster DSP capabilities
      2. Zynq-7000 SoC FPGA logic resources and DSP improvement
      3. Zynq-7000 SoC FPGA DSP slices
    2. DSP in an SoC and hardware acceleration mechanisms
      1. Accelerating DSP computation using the FPGA logic in FPGA-based SoCs
    3. Video and image processing implementation in FPGA devices and SoCs
      1. Xilinx AXI Video DMA engine
      2. Video processing systems generic architecture
      3. Using an SoC-based FPGA for edge detection in video applications
      4. Using an SoC-based FPGA for machine vision applications
    4. Summary
    5. Questions
  22. Chapter 14: Communication and Control Systems Implementation in FPGAs and SoCs
    1. Communication protocol layers
      1. OSI model layers overview
      2. Communication protocols topology
      3. Example communication protocols and mapping to the OSI model
    2. Communication protocol layers mapping onto FPGA-based SoCs
    3. Control systems overview
    4. Control system hardware and software mappings onto FPGA-based SoCs
    5. Summary
    6. Questions
  23. Index
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Product information

  • Title: Architecting and Building High-Speed SoCs
  • Author(s): Mounir Maaref
  • Release date: December 2022
  • Publisher(s): Packt Publishing
  • ISBN: 9781801810999