Technical requirementsMajor steps of the SoC software design flowETS SoC XSA archive file generation in the Vivado IDEETS SoC software project setup in Vitis IDEETS SoC MicroBlaze software project setup in the Vitis IDEETS SoC PS Cortex-A9 software project setup in the Vitis IDESetting up the BSP, boot software, drivers, and libraries for the software projectSetting up the BSP for the ETS SoC MicroBlaze PP application projectSetting up the BSP for the ETS SoC Cortex-A9 core0 application projectSetting up the BSP for the ETS SoC boot application projectDefining the distributed software microarchitecture for the ETS SoC processorsA simplified view of the ETS SoC hardware microarchitecture A summary of the data exchange mechanisms for the ETS SoC Cortex-A9 and the MicroBlaze IPC The ETMP protocol overviewThe ETS SoC system address mapThe Ethernet MAC and its DMA engine software control mechanismsThe AXI INTC software control mechanismsQuantitative analysis and system performance estimationThe ETS SoC Cortex-A9 software microarchitectureThe ETS SoC MicroBlaze PP software microarchitectureBuilding the user software applications to initialize and test the SoC hardwareSpecifying the linker script for the ETS SoC projectsSetting the compilation options and building the executable file for the Cortex-A9SummaryQuestions