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Architecting and Building High-Speed SoCs
book

Architecting and Building High-Speed SoCs

by Mounir Maaref
December 2022
Intermediate to advanced content levelIntermediate to advanced
426 pages
10h 40m
English
Packt Publishing
Content preview from Architecting and Building High-Speed SoCs

4

Connecting High-Speed Devices Using Buses and Interconnects

This chapter begins by giving an overview of the buses and interconnects used off-chip to connect an FPGA-based SoC to other high-speed devices on the electronics board. It introduces the PCIe interconnect, the Ethernet interconnect, and the emerging Gen-Z protocol. It also provides a good overview of the emerging CCIX interconnect protocol and the concept of extending data coherency off-chip by adding protocol layers in the SoC hardware to implement it.

In this chapter, we’re going to cover the following main topics:

  • An overview of the legacy off-chip interconnects
  • An introduction to the PCIe bus
  • An overview of the Ethernet interconnects
  • An introduction to the Gen-Z bus protocol ...
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Publisher Resources

ISBN: 9781801810999Supplemental Content