Architecture-Aware Optimization Strategies in Real-time Image Processing

3Rapid Prototyping of Parallel Reconfigurable Instruction Set Processor for Efficient Real-Time Image Processing

This chapter describes research results on enabling the reconfigurable instruction set processor (RISP) model for real-time image processing applications by exploiting FPGA technology. The aim is to keep the flexibility of processors in order to shorten the development cycle and at the same time profit from the powerful FPGA resources to increase realtime performance. Using advanced compiler technology, we designed modular RISP processor VHDL models with a variable instruction set and a customizable architecture which makes it possible to exploit the intrinsic parallelism of a target application and implement it in an optimal manner onto an FPGA. We illustrated the proposition by using the 2D spatial Cosine Transform algorithm with a variable block size on a Virtex-6-based board. Hardware implementations were realized in several ways by using either chip area or speed optimizations. Experimental results show that this approach applies some criteria to codesign tools: flexibility, modularity, performance and reusability.

3.1. Context and problematic

Adaptability of computing systems to support various multimedia formats and equipment with different computational requirements is highly desirable in the ubiquitous and seamless computing era. Currently, more and more image applications are choosing FPGAs as an implementation platform due to their flexibility and low ...