7Real-time Image Processing with Very High-level Synthesis

Programming in a high abstraction level can facilitate the development of digital single processing systems. A high-level synthesis technique greatly benefits the R&D productivity of the FPGA-based designs and helps add to the maintainability of the products by automating the C-to-RTL conversion. However, due to the high complexity and computational intensity, the image processing designs usually necessitate a higher abstraction level than C-synthesis, and the current HLS tools do not have the ability of this kind.

This chapter briefly presents a very high-level synthesis (VHLS) method that allows fast prototyping and verifying the desired FPGA-based image processing in the Matlab environment. A heterogeneous design flow by using currently available tool kits is built in order to synthesize the algorithm behavior from the user level into the low register transfer level. The main objective is again to further reduce the complexity of design and give play to the advantages of FPGA related to the other devices.

7.1. VHLS motivation

High abstraction level design flows have significant value. Since the 1990s, many efforts have been made to develop a production quality HLS method for FPGA designs. However, all the currently available HLS tools are based on C-synthesis techniques, whereas a higher abstraction level is usually required due to the high complexity and computationally intensity of the target algorithms. We attempt ...

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