Time is what prevents everything from happening at once.
—John Archibald Wheeler (1911– )
Dost thou love life? Then don't squander time, for that is the stuff life is made of.
We must use time as a tool, not as a couch.
—John F. Kennedy
Time is a great teacher, but unfortunately it kills all its pupils.
In previous chapters, synthesis of asynchronous circuits has been performed using very limited knowledge about the delays in the circuit being designed. Although this makes for very robust systems, a range of delay from 0 to infinity (as in the speed-independent case) is extremely conservative. It is quite unlikely that large functional units could respond after no delay. It is equally unlikely that gates and wires would take an infinite amount of time to respond. When timing information is known, this information can be utilized to identify portions of the state space which are unreachable. These unreachable states introduce additional don't cares in the logic synthesis problem, and they can be used to optimize the implementation that is produced. In this chapter we present a design methodology that utilizes known timing information to produce timed circuit implementations.
In this section we introduce semantics to support timing information during the synthesis process. This is done using a simple example.
Example 7.1.1 Consider the case where the shopkeeper actively calls the winery when he needs wine and ...