Computer Organization and Design RISC-V Edition

4

The Processor

Abstract

This chapter describes how processors exploit implicit parallelism. It contains an explanation of the principles and techniques used in implementing a processor, starting with a highly abstract and simplified overview. The overview is followed by a section that builds up a datapath and constructs a simple version of a processor sufficient to implement an instruction set like RISC-V. The bulk of the chapter covers a more realistic pipelined RISC-V implementation, and concludes with a section that develops the concepts necessary to implement more complex instruction sets, like x86.

Keywords

ARMv8; logic design; datapath; pipelining; control hazard; instruction-level parallelism; digital design; combinational element; ...