Computer Organization and Design MIPS Edition, 6th Edition

Figure e5.12.8 FSM in SystemVerilog, part IV.Actual FSM states via case statement in prior figure and this one. This figure has last part of the Compare Tag state, plus Allocate and Write-Back states.

Figures e5.12.1 and e5.12.2 declare the structures that are used in the definition of the cache in the following figures. For example, the cache tag structure (cache_tag_type) contains a valid bit (valid), a dirty bit (dirty), and an 18-bit tag field ([TAGMSB:TAGLSB] tag). Figure e5.12.3 shows the block diagram of the cache using the names from the Verilog description.

Figure e5.12.4 defines modules for the cache data (dm_cache_data) and cache tag ...