Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors

Chapter 9: Management of exceptions and interrupts

Abstract

This chapter describes the programmable registers available for interrupt and exception management, and the software interface available in CMSIS-CORE which make access to these management functions easier. Topics of interrupt masking registers, interrupt latency, and management of the exception vector table are also covered.

Keywords

Nested Vectored Interrupt Controller (NVIC); System Control Block (SCB); Interrupt masking registers; PRIMASK; FAULTMASK; BASEPRI; Vector table; Vector Table Offset Register (VTOR); Interrupt latency

9.1: Overview of exception and interrupt management

9.1.1: Access to exception management functions

Arm® Cortex®-M processors use a combination ...