book

Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors

Name: Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors
Author: Joseph Yiu
ISBN: 9780128207369

by Joseph Yiu

December 2020

Intermediate to advanced

928 pages

27h 40m

English

Newnes

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Cover image
Title page
Table of Contents
Copyright
Dedication
Preface
Contributing author: Paul Beckmann
Acknowledgments
Chapter 1: Introduction
Abstract1.1: Microcontrollers and processors1.2: Classification of processors1.3: The Cortex-M23 and Cortex-M33 processors and the Armv8-M architecture1.4: Characteristics of the Cortex-M23 and Cortex-M33 processors1.5: Why have two different processors?1.6: Applications of the Cortex-M23 and Cortex-M331.7: Technical features1.8: Comparison with previous generations of Cortex-M processors1.9: Advantages of the Cortex-M23 and Cortex-M33 processors1.10: Understanding microcontroller programming1.11: Further reading
Chapter 2: Getting started with Cortex-M programming
Abstract2.1: Overview2.2: Some basic concepts2.3: Introduction to Arm Cortex-M programming2.4: Software development flow2.5: Cortex Microcontroller Software Interface Standard (CMSIS)2.6: Additional information on software development

Chapter 3: Technical overview of the Cortex-M23 and Cortex-M33 processors
Abstract3.1: Design objectives of Cortex-M23 and Cortex-M33 processors3.2: Block diagrams3.3: Processor3.4: Instruction set3.5: Memory map3.6: Bus interfaces3.7: Memory protection3.8: Interrupt and exception handling3.9: Low power features3.10: OS support features3.11: Floating-point unit3.12: Coprocessor interface and Arm Custom Instructions3.13: Debug and trace support3.14: Multicore system design support3.15: Key feature enhancements in Cortex-M23 and Cortex-M33 processors3.16: Compatibility with other Cortex-M processors3.17: Processor configuration options3.18: Introduction to TrustZone3.19: Why TrustZone enables better security?3.20: Firmware asset protection with eXecute-Only-Memory (XOM)
Chapter 4: Architecture
Abstract4.1: Introduction to the Armv8-M architecture4.2: Programmer's model4.3: Memory system4.4: Exceptions and Interrupts4.5: Debug4.6: Reset and reset sequence4.7: Other related architecture information
Chapter 5: Instruction set
Abstract5.1: Background5.2: Instruction set features in various Cortex-M processors5.3: Understanding the assembly language syntax5.4: Use of a suffix in an instruction5.5: Unified Assembly Language (UAL)5.6: Instruction set—Moving data within the processors5.7: Instruction set—Memory access5.8: Instruction set—Arithmetic operations5.9: Instruction set—Logic operations5.10: Instruction set—Shift and rotate operations5.11: Instruction set—Data conversions (extend and reverse ordering)5.12: Instruction set—Bit field processing5.13: Instruction set—Saturation operations5.14: Instruction set—Program flow control
5.15: Instruction set—DSP extension
5.16: Instruction set—Floating point support instructions5.17: Instruction set—Exception-related instructions5.18: Instruction set—Sleep mode-related instructions5.19: Instruction set—Memory barrier instructions5.20: Instruction set—TrustZone support instructions5.21: Instruction set—Coprocessor and Arm custom instructions support5.22: Instruction set—Other functions5.23: Accessing special registers with the CMSIS-CORE
Chapter 6: Memory system
Abstract6.1: Overview of the memory system6.2: Memory map6.3: Memory types and memory attributes6.4: Access permission management6.5: Memory endianness6.6: Data alignment and unaligned data access support6.7: Exclusive access support6.8: Memory ordering and memory barrier instructions6.9: Bus wait state and error support6.10: Single-cycle I/O port—Cortex-M23 only6.11: Memory systems in microcontrollers6.12: Software considerations
Chapter 7: TrustZone support in the memory system
Abstract7.1: Overview7.2: SAU and IDAU7.3: Banked and nonbanked registers7.4: Test Target (TT) instructions and region ID numbers7.5: Memory protection controller and peripheral protection controller7.6: Security aware peripherals
Chapter 8: Exceptions and interrupts—Architecture overview
Abstract8.1: Overview of exceptions and interrupts8.2: Exception types8.3: Overview of interrupts and exceptions management8.4: Exception sequence introduction8.5: Definitions of exception priority levels8.6: Vector table and vector table offset register (VTOR)8.7: Interrupt input and pending behaviors8.8: Target states of exceptions and interrupts in TrustZone systems8.9: Stack frames8.10: EXC_RETURN8.11: Classification of synchronous and asynchronous exceptions
Chapter 9: Management of exceptions and interrupts
Abstract9.1: Overview of exception and interrupt management9.2: Details of the NVIC registers for interrupt management9.3: Details of SCB registers for system exception management9.4: Details of special registers for exception or interrupt masking9.5: Vector table definition in programming9.6: Interrupt latency and exception handling optimizations9.7: Tips and hints
Chapter 10: Low power and system control features
Abstract10.1: The quest for low power10.2: Low power features in the Cortex-M23 and Cortex-M33 processors10.3: More on WFI, WFE, and SEV instructions10.4: Developing low power applications10.5: System Control Block (SCB) and system control features10.6: Auxiliary Control Register10.7: Other registers in the System Control Block
Chapter 11: OS support features
Abstract11.1: Overview of the OS support features11.2: SysTick timer11.3: Banked stack pointers11.4: Stack limit checking11.5: SVCall and PendSV exceptions11.6: Unprivileged execution level and the Memory Protection Unit (MPU)11.7: Exclusive access11.8: How should an RTOS run in a TrustZone environment?11.9: Concepts of RTOS operations in Cortex-M processors
Chapter 12: Memory Protection Unit (MPU)
Abstract12.1: Overview of the MPU12.2: MPU registers12.3: Configuration of the MPU12.4: TrustZone and MPU12.5: Key differences between the MPU in Armv8-M architecture and the architecture of the previous generations
Chapter 13: Fault exceptions and fault handling
Abstract13.1: Overview13.2: Cause of faults13.3: Enabling fault exceptions13.4: Fault handler designs considerations13.5: Fault status and other information13.6: Lockup13.7: Analysis of fault events13.8: Stack trace13.9: Fault handler to extract stack frame and display fault status
Chapter 14: The Floating-Point Unit (FPU) in the Cortex-M33 processor
Abstract14.1: Floating-point data14.2: Cortex-M33 Floating-point Unit (FPU)14.3: Key differences between the FPUs of the Cortex-M33 FPU and the Cortex-M414.4: Lazy stacking in details14.5: Using the FPU14.6: Floating-point exceptions14.7: Hints and tips
Chapter 15: Coprocessor interface and Arm Custom Instructions
Abstract15.1: Overview15.2: Overview of the architecture15.3: Accessing coprocessor instructions via intrinsic functions in C15.4: Accessing Arm Custom Instructions via the intrinsic functions in C15.5: Software steps to take when enabling the coprocessor and the Arm Custom Instructions15.6: Coprocessor power control15.7: Hints and tips
Chapter 16: Introduction to the debug and trace features
Abstract16.1: Introduction16.2: Debug architecture details16.3: An introduction to debug components16.4: Starting a debug session16.5: Flash memory programming support16.6: Software design considerations
Chapter 17: Software development
Abstract17.1: Introduction17.2: Getting started with the Keil Microcontroller Development Kit (MDK)17.3: Procedure Call Standard for the Arm Architecture17.4: Software scenarios
Chapter 18: Secure software development
Abstract18.1: Overview of Secure software development18.2: TrustZone technical details18.3: Secure software development18.4: Creating a Secure project in Keil MDK18.5: CMSE support in other toolchains18.6: Secure software design considerations
Chapter 19: Digital signal processing on the cortex-M33 processor
Abstract19.1: DSP on a microcontroller?19.2: Why use a Cortex-M processor for a DSP application?19.3: Dot product example19.4: Getting more performance by utilizing the SIMD instructions19.5: Dealing with overflows19.6: Introduction to data types for signal processing19.7: Cortex-M33 DSP instructions19.8: Writing optimized DSP code for the Cortex-M33 processor
Chapter 20: Using the Arm CMSIS-DSP library
Abstract20.1: Overview of the library20.2: Function naming convention20.3: Getting help20.4: Example 1—DTMF demodulation20.5: Example 2—Least squares motion tracking20.6: Example 3—Real-time filter design20.7: How to determine the implemented instruction set features in a Cortex-M33 based system
Chapter 21: Advanced topics
Abstract21.1: Further information on stack memory protection21.2: Semaphores, load-acquire and store-release instructions21.3: Unprivileged interrupt handler21.4: Re-entrant interrupt handler21.5: Software optimization topics
Chapter 22: Introduction to IoT security and the PSA Certified™ framework
Abstract22.1: From processor architecture to IoT security22.2: Introduction of PSA Certified22.3: The Trusted Firmware-M (TF-M) project22.4: Additional information
Index

Content preview from Definitive Guide to Arm Cortex-M23 and Cortex-M33 Processors

Chapter 14: The Floating-Point Unit (FPU) in the Cortex-M33 processor

Abstract

This chapter describes the Floating-Point Unit (FPU) in the Cortex-M33 processor. It starts by introducing the floating-point data formats, then covers FPU topics, including the range of FPU features, the programmer's model and configurations. The topic of lazy stacking, a feature that helps avoid unnecessary latency when dealing with interrupts, is also explained. Finally, a range of areas that software developers need to know in order to utilize the FPU features are highlighted.

Keywords

Floating-point unit (FPU); Half precision; Single precision; Double precision; Lazy stacking; Floating-point exception; Application Binary Interface (ABI); FPU modes

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