Design for Embedded Image Processing on FPGAs, 2nd Edition

4Design Constraints

Chapter 3 described the process of designing an embedded image processing application for implementation on a field‐programmable gate array (FPGA). Part of the implementation process involves mapping the algorithm onto the resources of the FPGA. Four types of constraints to this mapping process were identified as timing (limited processing time), memory bandwidth (limited access to data), resource (limited system resources), and power (limited available energy) constraints (Gribbon et al., 2005, 2006). In this chapter, a selection of techniques for overcoming or alleviating these constraints will be described in more detail.

The requirements analysis phase may also identify performance constraints. This chapter concludes with definitions of common performance metrics, both of the implementation and the application.

4.1 Timing Constraints

The data rate requirements of real‐time applications impose a strict timing constraint. These are of two types: throughput and latency.

Throughput is the rate at which data must be processed. Stream processing has a strict throughput constraint, usually of one pixel every clock cycle. If this processing rate is not maintained, then data streamed from the camera may be lost, or data streamed to the display may be missing. The clock frequency imposes a timing constraint on the maximum propagation delay between registers within an RTL design. Since the processing per pixel of many image processing operations takes longer ...