Design for Embedded Image Processing on FPGAs, 2nd Edition

15Example Applications

In the earlier chapters, much of the focus in describing field‐programmable gate array (FPGA) implementation was on individual image processing operations, rather than complete applications. This final chapter shows how the individual operations tie together within an application. Of particular interest are some of the optimisations used to reduce hardware or processing time.

15.1 Coloured Region Tracking

The desire in this application was to use coloured paddles to create a gesture‐based user input (Johnston et al., 2005b). A secondary goal was to minimise resource utilisation to enable the remainder of the FPGA to be used for the application being controlled (Johnston et al., 2005a).

The basic structure of the algorithm is shown in Figure 15.1. The distinctive colours of the paddles are used to segment them from the background. A simple bounding box is then used to determine the paddle locations. The remainder of this section details the algorithm and the optimisations made to reduce the size of the implementation.

This application was originally implemented on an RC100 board from Celoxica Ltd. The board used a Xilinx XC2S200 Spartan II FPGA, quite small, with very limited resources by modern standards. The live video was captured using a video decoder chip which digitises the composite video signal from the camera and provides a stream of 16‐bit colour (RGB565) pixels to the FPGA. The decoder provides a 27‐MHz pixel clock, with one pixel streamed ...