As shown in Section 4.3, to realize multiple sub-bands for the proposed
inductor-loaned transformer, switches are loaded at various locations on the
secondary coil of one transformer. As the number of switches increases, the
total capacitance and resistance loaded on the transformer increases and
decreases, respectively. According to the analysis in Sec tion 4.2.2, for the
conditions when switches are turned oﬀ, both a larger C and a smaller
R would weaken the domination of the terms R
[1 − ω
(1 − k
1 − ω
1 − ω
1 − k
in (1), resulting in a smaller FTR. As
a result, the number of switches loaded on the transformer should be mini-
mized while providing enough sub-bands .
As a res ult, one layout topology is designed in this section, w hich can re-
alize the maximum number of sub-bands with the least number of switches,
thus can achieve the maximized FTR. The penalty is an asymmetric layout
implementation, which may cause ce rtain degradation in the phase noise per-
formance. This problem can be solved with another symmetric topology to be
presented in Section 4.4.3.
184.108.40.206 60-GHz VCO Design
Loaded Transformer Design
The proposed topology targets the maximum FTR, with layout implementa-
tion shown in Figure 4.14. A transformer is lo aded w ith 4 switches (S1˜S4)
at diﬀerent locations. The inner loop is the primary c oil, which serves as the
inductor of the LC-tank. The outer loop is the secondary coil, which is loaded
with 4 switches to control the cur rent return-pa ths. Lengths of the 4 sections
in the secondary coil are marked with unit length l. Diﬀerent combinations of
the switches and corresponding eﬀective lengths of the current return-paths
are summarized in Ta ble 4.7. There are in total 7 modes or sub-bands estab-
lished. For exa mple, by turning on switches S1 and S2, the mode 3 is invoked
with a current return-path formed with length 3l. Moreover, as shown in Ta-
ble 4.7, the eﬀective length of r eturn-path in secondary coil varies from 0 to
6l linearly, resulting in 7 evenly distributed sub-bands. Evenly distributed
sub-binds can facilitate PLL design and also improve its performance.
Note that more sub-bands can be realized by implementing more switches
but may also degrade the pha se noise performance. As derived in Section 4.2.2
and 4.3, a small switch R value is desired to minimize phase noise degradation.
As such, the number of switches should be minimized when connected in serial
in the activated current return-path. The proposed band selection method in
Figure 4.14 and Table 4.7 can minimize the number of switches in the current
return-path to be 2 or be low for all selection modes.
With an asymmetric allocation of switches, this layout implementation
realizes 7 sub-bands with only 4 switches. As a result, a maximized FTR can
be achieved. The trade-oﬀ is that the asymmetric twitch locations and cur rent
return-paths would have a large phase noise variation due to diﬀerent current
return-paths in each sub-band.