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Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits with Metamaterials by Yang Shang, Hao Yu

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148 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
As such, all combined transistors can be periodically loaded in the combining
network where their output powers are merg ed in phase. Unfortunately, in
many power combiner topologies, a long T-line proportional to wavelength
(λ) is often re quired to achieve the in-phase power co mbining of transistors.
Since advanced technology only scales active devices while the passive devices
remain relatively the same s ize, the power combiner size is normally domi-
nated by the passive elements. As a result, due to the usage of a long RH
T-line, high output power normally leads to bulky combiner size w hich is not
appealing for mm-wave system integration. On the other hand, CRLH T-line
with its unique phase-change property could be used to replace the RH T-line
with the same chase requirement but much more compact size and lower loss.
In the following section, an active in-phase distributed CRLH T-line network
is proposed to improve the power combining efficiency and with high output
power and high output power density achieved simultaneously at mm-wave
frequency region.
7.2 In-Ph ase Signal Transmission by CRLH
Zero-Phase-Shifter
In order to achieve high output power/output power density performance with
improved power combining efficiency and wide bandwidth, multiple transistors
need to be periodically loaded in the combining network in compact size with
distributed topology where the output power of each transistor is combined in
phase. With a compact CRLH T-line to re place the traditional RH T-line, the
challenge is how to load transistors in T-line network and have their output
power combined in pha se. The loading method for traditional active CRLH T-
line is not feasible for PA desig n as a negative resistor would pause oscillation.
Alternatively, transistor output power can be in-phase combined by directly
connecting their outputs with zero-phase connections, which can be realized
by the CRLH T-line-based zero-phase-shifter (ZPS) with transistor parasitic
absorbed into the T-line design. Since zero- phase CRLH T-line can realize
in-phase power co mbining both in parallel and in series, a 2D active CRLH
T-line network is introduced in Figure 7.1.
As shown in Figure 7.1, the power combining is achieved in 2 levels: serial
power combining (1
st
level) realized in ea ch branch; and parallel power com-
bining (2
nd
level) further implemented at the output. Active CRLH T-line unit
cells ar e realized by absorbing the parasitic capac itance of the loaded tran-
sistors into design. In the 1
st
level combining, by designing the active CRLH
T-line with zero-phase-shift in the targe t frequency, all transistor outputs in
each branch can be serially combined in phase. The load-pull optimization pro-
cess is also simplified as load-line impedance of all transistors can be viewed
directly fed to output. As a result, the optimized power performa nc e can be
achieved by simply feeding a load impedance R
g
=R
opt
/N to the output of the
Power Combiner 149
Figure 7.1: Propo sed 2D active CRLH T-line network. By absorb-
ing parasitic C from transistors into zero-phase CRLH T-line design,
in-phase power combining is realized both in series and in parallel,
resulting 2D distributes power combining.
branch, where R
opt
is the optimized load-line impedance which can be easily
calculated. For example, for class-A amplifier design, the o ptimized efficiency
can be a chieved by implementing: R
opt
= (V
max
V
min
)/I
max
, where V
max
and V
min
are the maximum and minimum output voltage of transistors for
class A operation and I
max
is the maximum output current [200].
Due to the power pre-combining in the 1
st
level, the size of the parallel
power combiner in the 2
nd
level ca n be largely re duced with use of compact
transformers, which perform output matching at the same time. Moreover,
a differential structure could be implemented in bo th CRLH T-line and PA
with benefits of compact size and reduced loss. As a result, more (>10) power
transistors can be combined for high output power with high power combining
efficiency and wide bandwidth.
Note there may be various connection methods to achieve in-phase power
combining using CRLH T-line-based ZPS. However, the exact zero-phase-shift
is only realized at one frequency point. To achieve wide -band performance, the
ZPS connections for the seria l power combining is adjusted to resemble one
distributed amplification topology named single-e nded dual-fed distributed
amplifier (SEDFDA) topology [9], but with the bulky λ/2 T-line replaced with
compact zero-phase CRLH T-line, thus achieving wide bandwidth with much

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