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Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits with Metamaterials by Yang Shang, Hao Yu

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244 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 1 0.12: Schematic of CMOS 135 GHz SRX with DTL-SRR.
M1 for the electrostatic discharge (ESD) pr otection when integrating with the
antenna; sec ondly, the virtual ground formed by two λ/4 T-lines is replaced
by the high-Q MOM capacitor to further reduce the chip area; thirdly, the
detected envelope signal V
ENV
is directly averaged by an on-chip low-pass
filter formed by R3 and C3 at the output.
10.4 Circuit Prototyping and Measureme nt
10.4.1 DTL-CSRR-Based SRX at 96 GHz
As shown in Figure 10.13(a), the proposed DTL-CSRR-based SRX is imple-
mented in the UMC 65-nm CMOS process with f
T
/f
MAX
of 170/190 GHz.
The total die area is 500 × 440 µm
2
including a core area of 0.014 mm
2
with
resonator and active devices. The SRX is measur ed o n probe station (CAS-
CADE Microtech Elite-300) with RF input signal provided by Agilent PNA-X
(N5247A) with T /R modules (N5260), of which the output power is calibrated
in the range of -8 5 -10 dBm by Agilent Spectrum Analyzer E4407B with a
W-band waveguide harmonic mixer (11970W). Note that the output power of
the T/R module can be controlled by N5247A, but its minimum output power
Super-Regenerative Detection 245
Figure 10.13: Die micrographs: (a) CMOS 96 GHz SRX with DTL-
CSRR, and (b) CMOS 135 GHz SRX with DTL-SRR.
level that can be calibrated is limited by the sensitivity of spectrum analyzer.
A 12.5MHz sinusoid quench-control signal is applied by function generator
(AFG302 2) with voltage swept in 0 250 mV. The receiver operates under
1-V power supply w ith a power consumption of 2.8 mW.
The receiver g ain is defined a s Gain(dB) = 20 log V
out
P
in
, where V
out
is the normalized output voltage of receiver and P
in
is the input power level
of proposed SRX in dBm. The a ctual gain of SRX is no t totally independent
of P
in
as discussed in (10.6) in Sec. 10.2. A relative higher P
in
of -20 dBm is
applied to have sufficient V
out
at the frequency outside the bandwidth. Figure
10.14(a) shows the measured and simulated gain and input S11, where the
maximum gain of proposed SRX at -20-dBm P
in
is 21 dB at 95.5 GHz and
a 3-dB bandwidth o f 560 MHz is observed. The measured gain is quite close
to the postlayout simulation result. A g ood input match is also obser ved with
S11 smaller than -14 dB from 94.6 GHz to 96.6 GHz. Fig ure 10.14(b) shows
the no rmalized V
out
against P
in
as well as the respons ivity, where an almost
linear response is observed with a sensitivity of -78 dBm and a maximum
responsivity of 6.02 MV/W. Note that responsivity is calculated by V
out
/P
in
.
The mea sured responsivity is very clo se to the simulation results esp ecially
when the input power level is below -70dBm. The noise equivalent power
(NEP) of proposed SRX is 0.67 fW/
Hz, which is calculated by S/
B,
where S is the sensitivity and B is the 3-dB bandwidth [89]. Finally, the noise
figure (NF) is found to be 8.5 dB by S/(K · T · B) a t room temperature of
290K.
246 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
(a)
(b)
Figure 10.14: Measurement and simulation results of CMOS 96 GHz
SRX. (a) gain and input S11, and (b) output voltage (V
out
) and re-
sponsivity vs. input power (P
in
).
10.4.2 DTL-SRR-Based SRX at 135 GHz
As shown in Figur e 10.13(b), the proposed DTL-SRR-based SRX is imple-
mented in Glo bal Foundries 65-nm CMOS RF process with f
T
/f
MAX
of

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