Chapter 14
CMOS THz Wireline
Communicat i on
14.1 Introduction
Future high-performance computers require wide-ba nd on-chip communica-
tion between memory and microprocessor cores. The globa l interconnect by
top-layer metal in prese nt CMOS technology has limited bandwidth and large
crosstalk ratio [283, 284]. The lossy substrate with typical 10 -Ω/cm resistivity
introduces a low-impedance path betwee n metal and substrate, r esulting in
narrow bandwidth and high loss. Moreover, at high operating fr equency the
current flow tends to crowd toward the surface of metal due to proximity ef-
fect, which leads to not only higher ohmic loss but also large electromagnetic
coupling. As such, the CMOS metal-based interconnect is not scalable to pro-
vide wide bandwidth for on-chip communication beyond gigabit per second
(Gbps) for one channel.
Though the optical interconnect has shown great potential to replac e elec-
trical interconnects [285, 286], its source, transmission and detection are all
difficult to be implemented in silicon. Terahertz (THz) ba nds have recently
attracted great interest because all components can be realized in CMOS tech-
nology [93, 287]. However, highly integrated on-chip high-s peed interconnects
by traditional transmission lines (T-lines) have the limitation o f crosstalk be-
tween two adjacent channels.
Due to the neg ative permittivity behavior [288, 289, 290], surface plas-
mon p olariton (SPP) is one special electromagnetic wave locally confined
on the meta l/dielectric interface, pro pagating in parallel to the interface
and exponentially decaying in the direc tion perpendicular to the interface
298 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Conventional T-line
SPP T-Line
Substrate loss
Figure 14.1: The layout and E-fie ld distribution o f the on -chip
SPP/conventional T-line in lossy substrate environment, d, h, a, w
denotes the periodic pitch, groove depth, groove width and line width
off SPP T-line, respectively. The magnetic field of SPP T-li ne is di-
rected to the x direction while the electrical field is guided by the
grooves in the y-z plane.
[291, 292, 293]. By introducing sub-wavelength periodic corrugation structure
onto the T-line, SPPs can be established to propagate signals with strongly
localized surface-wave in the metal/dielectric interface at frequency up to
THz. Such a surface-wave can be supported with propagation adapted to the
curvature or holes of the surface [294, 169, 295, 296, 297, 298, 299, 30 0, 301].
Previous works have demonstrated GHz SPP T-lines on board level with bulky
size and loss [294, 169, 295, 296, 297, 298]. In this work, SPP T-line is inves-
tigated at the THz region in the standard CMOS process that shows great
potential for system-on-chip integration with other components in CMOS for
on-chip THz communication.
The physical layout of the proposed structure is illustrated in Figure 14.1.
Two on-chip SPP T-lines are placed back-to-back to form a broadband low-
loss, low-cr osstalk coupler. Such a plasmonic metamaterial consists of a metal
strip with thin film thickness, in which a 1D periodical a rray of grooves is
drilled. The propagatio n of surface-confined mode is adapted to the curva-
ture of the surface, and the resulting cr osstalk between the two back-to-back
placed SPP T-lines will be reduced significantly. For comparison, two tradi-
tional quasi-TEM T-lines are also realized to form an on-chip coupler with
line space of 2.4 µm in standard 65 nm CMOS process, which shows la rge loss
and strong crosstalk at THz. Measurement results show that the SPP T-lines
achieve wide-band reflection coefficient lower than -14 dB and the crosstalk
ratio better than -24 dB, which is 19 dB lower on average than the traditional
T-lines from 220 GHz to 325 GHz. The compact and wide -band SPP T-lines
have shown great potential for on-chip THz communication.

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