Design Recipes for FPGAs, 2nd Edition

Design Recipes for FPGAs, 2nd Edition

by Peter Wilson
Released October 2015
Publisher(s): Newnes
ISBN: 9780080971360

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Book description

Design Recipes for FPGAs provides a rich toolbox of design techniques and templates to solve practical, every-day problems using FPGAs. Using a modular structure, it provides design techniques and templates at all levels, together with functional code, which you can easily match and apply to your application. Written in an informal and easy to grasp style, this invaluable resource goes beyond the principles of FPGAs and hardware description languages to demonstrate how specific designs can be synthesized, simulated and downloaded onto an FPGA. In addition, the book provides advanced techniques to create ‘real world’ designs that fit the device required and which are fast and reliable to implement.

  • Examples are rewritten and tested in Verilog and VHDL
  • Describes high-level applications as examples and provides the building blocks to implement them, enabling the student to start practical work straight away
  • Singles out the most important parts of the language that are needed for design, giving the student the information needed to get up and running quickly

Table of contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. Copyright
  5. Preface to the Second Edition
  6. Preface to the First Edition
  7. Acknowledgments
  8. Part 1: Overview
    1. Introduction
    2. Chapter 1: Introduction
      1. Abstract
      2. 1.1 Overview
      3. 1.2 Verilog vs. VHDL
      4. 1.3 Why FPGAs?
      5. 1.4 Summary
    3. Chapter 2: An FPGA Primer
      1. Abstract
      2. 2.1 Introduction
      3. 2.2 FPGA Evolution
      4. 2.3 Programmable Logic Devices
      5. 2.4 Field Programmable Gate Arrays
      6. 2.5 FPGA Design Techniques
      7. 2.6 Design Constraints using FPGAs
      8. 2.7 Development Kits and Boards
      9. 2.8 Summary
    4. Chapter 3: A VHDL Primer: The Essentials
      1. Abstract
      2. 3.1 Introduction
      3. 3.2 Entity: Model Interface
      4. 3.3 Architecture: Model Behavior
      5. 3.4 Process: Basic Functional Unit in VHDL
      6. 3.5 Basic Variable Types and Operators
      7. 3.6 Decisions and Loops
      8. 3.7 Hierarchical Design
      9. 3.8 Debugging Models
      10. 3.9 Basic Data Types
      11. 3.10 Summary
    5. Chapter 4: A Verilog Primer: The Essentials
      1. Abstract
      2. 4.1 Introduction
      3. 4.2 Modules
      4. 4.3 Connections
      5. 4.4 Wires and Registers
      6. 4.5 Defining the Module Behavior
      7. 4.6 Parameters
      8. 4.7 Variables
      9. 4.8 Data Types
      10. 4.9 Decision Making
      11. 4.10 Loops
      12. 4.11 Summary
    6. Chapter 5: Design Automation of FPGAs
      1. Abstract
      2. 5.1 Introduction
      3. 5.2 Simulation
      4. 5.3 Libraries
      5. 5.4 std_logic Type Definition
      6. 5.5 Synthesis
      7. 5.6 RTL Design Flow
      8. 5.7 Physical Design Flow
      9. 5.8 Place and Route
      10. 5.9 Timing Analysis
      11. 5.10 Design Pitfalls
      12. 5.11 Summary
    7. Chapter 6: Synthesis
      1. Abstract
      2. 6.1 Introduction
      3. 6.2 Numeric Types
      4. 6.3 Wait Statements
      5. 6.4 Assertions
      6. 6.5 Loops
      7. 6.6 Some Interesting Cases Where Synthesis May Fail
      8. 6.7 What Is Being Synthesized?
      9. 6.8 Summary
  9. Part 2: Introduction to FPGA Applications
    1. Introduction
    2. Chapter 7: High Speed Video Application
      1. Abstract
      2. 7.1 Introduction
      3. 7.2 The Camera Link Interface
      4. 7.3 Getting Started
      5. 7.4 Specifying the Interfaces
      6. 7.5 Defining the Top Level Design
      7. 7.6 System Block Definitions and Interfaces
      8. 7.7 The Camera Link Interface
      9. 7.8 The PC Interface
      10. 7.9 Summary
    3. Chapter 8: Simple Embedded Processors
      1. Abstract
      2. 8.1 Introduction
      3. 8.2 A Simple Embedded Processor
      4. 8.3 A Simple Embedded Processor Implemented in VHDL
      5. 8.4 A Simple Embedded Processor Implemented in Verilog
      6. 8.5 Soft Core Processors on an FPGA
      7. 8.6 Summary
  10. Part 3: Designer’s Toolbox
    1. Introduction
    2. Chapter 9: Digital Filters
      1. Abstract
      2. 9.1 Introduction
      3. 9.2 Converting S Domain to Z Domain
      4. 9.3 Implementing Z Domain Functions in VHDL
      5. 9.4 Basic Low Pass Filter Model
      6. 9.5 Implementing Z Domain Functions in Verilog
      7. 9.6 Finite Impulse Response Filters
      8. 9.7 Infinite Impulse Response Filters
      9. 9.8 Summary
    3. Chapter 10: Secure Systems
      1. Abstract
      2. 10.1 Introduction to Block Ciphers
      3. 10.2 Feistel Lattice Structures
      4. 10.3 The Data Encryption Standard (DES)
      5. 10.4 Advanced Encryption Standard
      6. 10.5 Summary
    4. Chapter 11: Memory
      1. Abstract
      2. 11.1 Introduction
      3. 11.2 Modeling Memory in HDLs
      4. 11.3 Read Only Memory
      5. 11.4 Random Access Memory
      6. 11.5 Synchronous RAM
      7. 11.6 Flash Memory
      8. 11.7 Summary
    5. Chapter 12: PS/2 Mouse Interface
      1. Abstract
      2. 12.1 Introduction
      3. 12.2 PS/2 Mouse Basics
      4. 12.3 PS/2 Mouse Commands
      5. 12.4 PS/2 Mouse Data Packets
      6. 12.5 PS/2 Operation Modes
      7. 12.6 PS/2 Mouse with Wheel
      8. 12.7 Basic PS/2 Mouse Handler VHDL
      9. 12.8 Modified PS/2 Mouse Handler VHDL
      10. 12.9 Basic PS/2 Mouse Handler in Verilog
      11. 12.10 Summary
    6. Chapter 13: PS/2 Keyboard Interface
      1. Abstract
      2. 13.1 Introduction
      3. 13.2 PS/2 Keyboard Basics
      4. 13.3 PS/2 Keyboard Commands
      5. 13.4 PS/2 Keyboard Data Packets
      6. 13.5 PS/2 Keyboard Operation Modes
      7. 13.6 Summary
    7. Chapter 14: A Simple VGA Interface
      1. Abstract
      2. 14.1 Introduction
      3. 14.2 Basic Pixel Timing
      4. 14.3 Image Handling
      5. 14.4 A VGA Interface in VHDL
      6. 14.5 A VGA Interface in Verilog
      7. 14.6 Summary
    8. Chapter 15: Serial Communications
      1. Abstract
      2. 15.1 Introduction
      3. 15.2 Manchester Encoding and Decoding
      4. 15.3 Implementing the Manchester Encoding Scheme using VHDL
      5. 15.4 Implementing the Manchester Encoding Scheme using Verilog
      6. 15.5 NRZ (Non-Return-to-Zero) Coding and Decoding
      7. 15.6 NRZI (Non-Return-to-Zero-Inverted) Coding and Decoding
      8. 15.7 RS-232
      9. 15.8 Universal Serial Bus
      10. 15.9 Summary
  11. Part 4: Optimizing Designs
    1. Introduction
    2. Chapter 16: Design Optimization
      1. Abstract
      2. 16.1 Introduction
      3. 16.2 Techniques for Logic Optimization
      4. 16.3 Improving Performance
      5. 16.4 Critical Path Analysis
      6. 16.5 Summary
    3. Chapter 17: Behavioral Modeling in using HDLs
      1. Abstract
      2. 17.1 Introduction
      3. 17.2 How to Go from RTL to Behavioral HDL Descriptions
      4. 17.3 Implementing the Behavioral Model using VHDL
      5. 17.4 Implementing the Behavioral Model using Verilog
      6. 17.5 Summary
    4. Chapter 18: Mixed Signal Modeling
      1. Abstract
      2. 18.1 Introduction
      3. 18.2 Basic Modeling Approach for VHDL-AMS
      4. 18.3 Introduction to VHDL-AMS
      5. 18.4 VHDL-AMS Analog Pins: TERMINALS
      6. 18.5 Mixed Domain Modeling
      7. 18.6 VHDL-AMS Analog Variables: Quantities
      8. 18.7 Simultaneous Equations in VHDL-AMS
      9. 18.8 A VHDL-AMS Example: A DC Voltage Source
      10. 18.9 A VHDL-AMS Example: Resistor
      11. 18.10 Differential Equations in VHDL-AMS
      12. 18.11 Mixed-Signal Modeling with VHDL-AMS
      13. 18.12 A Basic Switch Model
      14. 18.13 Basic VHDL-AMS Comparator Model
      15. 18.14 Multiple Domain Modeling
      16. 18.15 Introduction to Verilog-AMS
      17. 18.16 Verilog-AMS: Analog ports
      18. 18.17 Mixed Domain Modeling in Verilog-AMS
      19. 18.18 Verilog-AMS Analog Variables
      20. 18.19 Verilog-AMS Analog Equations
      21. 18.20 A Verilog-AMS Example
      22. 18.21 Differential Equations in Verilog-AMS
      23. 18.22 Mixed Signal Modeling with Verilog-AMS
      24. 18.23 Multiple Domain Modeling using Verilog-AMS
      25. 18.24 Summary
    5. Chapter 19: Design Optimization Example: DES
      1. Abstract
      2. 19.1 Introduction
      3. 19.2 The Data Encryption Standard
      4. 19.3 MOODS
      5. 19.4 Initial Design
      6. 19.5 Initial Synthesis
      7. 19.6 Optimizing the Datapath
      8. 19.7 Final Optimization
      9. 19.8 Results
      10. 19.9 Triple DES
      11. 19.10 Comparing the Approaches
      12. 19.11 Summary
  12. Part 5: Fundamental Techniques
    1. Introduction
    2. Chapter 20: Latches, Flip-Flops, and Registers
      1. Abstract
      2. 20.1 Introduction
      3. 20.2 Latches
      4. 20.3 Flip-Flops
      5. 20.4 Registers
      6. 20.5 Summary
    3. Chapter 21: ALU Functions
      1. Abstract
      2. 21.1 Introduction
      3. 21.2 Logic Functions in VHDL
      4. 21.3 Structural n-Bit Addition
      5. 21.4 Logic Functions in Verilog
      6. 21.5 Configurable n-Bit Addition
      7. 21.6 Two’s Complement
      8. 21.7 Summary
    4. Chapter 22: Finite State Machines in VHDL and Verilog
      1. Abstract
      2. 22.1 Introduction
      3. 22.2 State Transition Diagrams
      4. 22.3 Implementing Finite State Machines in VHDL
      5. 22.4 Implementing Finite State Machines in Verilog
      6. 22.5 Testing the Finite State Machine Model
      7. 22.6 Summary
    5. Chapter 23: Fixed Point Arithmetic
      1. Abstract
      2. 23.1 Introduction
      3. 23.2 Basic Fixed Point Types in VHDL
      4. 23.3 Fixed Point Functions in VHDL
      5. 23.4 Testing the VHDL Fixed Point Functions
      6. 23.5 Fixed Point Types in Verilog
      7. 23.6 Floating Point Types in Verilog
      8. 23.7 Summary
    6. Chapter 24: Counters
      1. Abstract
      2. 24.1 Introduction
      3. 24.2 Basic Binary Counter using VHDL
      4. 24.3 Simple Binary Counter using Verilog
      5. 24.4 Synthesized Simple Binary Counter
      6. 24.5 Shift Register
      7. 24.6 The Johnson Counter
      8. 24.7 BCD Counter
      9. 24.8 Summary
    7. Chapter 25: Decoders and Multiplexers
      1. Abstract
      2. 25.1 Decoders
      3. 25.2 Multiplexers
      4. 25.3 Summary
    8. Chapter 26: Multiplication
      1. Abstract
      2. 26.1 Introduction
      3. 26.2 Basic Binary Multiplication
      4. 26.3 VHDL Unsigned Multiplier
      5. 26.4 Synthesis of the Multiplication Function
      6. 26.5 Simple Multiplication using VHDL
      7. 26.6 Simple Multiplication using Verilog
      8. 26.7 Summary
    9. Chapter 27: Simple 7-Segment (LCD) Displays
      1. Abstract
      2. 27.1 Introduction
      3. 27.2 VHDL LCD Module Decoder
      4. 27.3 Verilog LCD Module Decoder
      5. 27.4 Summary
  13. Bibliography
    1. Introduction
    2. Useful Texts for VHDL
    3. Useful Texts for Verilog
    4. Useful Texts for FPGAs
    5. General Digital Design Books
  14. Index

Product information

  • Title: Design Recipes for FPGAs, 2nd Edition
  • Author(s): Peter Wilson
  • Release date: October 2015
  • Publisher(s): Newnes
  • ISBN: 9780080971360