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Design Recipes for FPGAs, 2nd Edition

Name: Design Recipes for FPGAs, 2nd Edition
Author: Peter Wilson
ISBN: 9780080971360

by Peter Wilson

October 2015

Intermediate to advanced

392 pages

8h 52m

English

Newnes

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Cover image
Title page
Table of Contents
Copyright
Preface to the Second Edition
Preface to the First Edition
Acknowledgments
Part 1: Overview
Introduction
Chapter 1: Introduction
Abstract1.1 Overview1.2 Verilog vs. VHDL1.3 Why FPGAs?1.4 Summary

Chapter 2: An FPGA Primer
Abstract2.1 Introduction2.2 FPGA Evolution2.3 Programmable Logic Devices2.4 Field Programmable Gate Arrays2.5 FPGA Design Techniques2.6 Design Constraints using FPGAs2.7 Development Kits and Boards2.8 Summary
Chapter 3: A VHDL Primer: The Essentials
Abstract3.1 Introduction3.2 Entity: Model Interface3.3 Architecture: Model Behavior3.4 Process: Basic Functional Unit in VHDL3.5 Basic Variable Types and Operators3.6 Decisions and Loops3.7 Hierarchical Design3.8 Debugging Models3.9 Basic Data Types3.10 Summary
Chapter 4: A Verilog Primer: The Essentials
Abstract4.1 Introduction4.2 Modules4.3 Connections4.4 Wires and Registers4.5 Defining the Module Behavior4.6 Parameters4.7 Variables4.8 Data Types4.9 Decision Making4.10 Loops4.11 Summary
Chapter 5: Design Automation of FPGAs
Abstract5.1 Introduction5.2 Simulation5.3 Libraries5.4 std_logic Type Definition5.5 Synthesis5.6 RTL Design Flow5.7 Physical Design Flow5.8 Place and Route5.9 Timing Analysis5.10 Design Pitfalls5.11 Summary
Chapter 6: Synthesis
Abstract6.1 Introduction6.2 Numeric Types6.3 Wait Statements6.4 Assertions6.5 Loops6.6 Some Interesting Cases Where Synthesis May Fail6.7 What Is Being Synthesized?6.8 Summary
Part 2: Introduction to FPGA Applications
Introduction
Chapter 7: High Speed Video Application
Abstract7.1 Introduction7.2 The Camera Link Interface7.3 Getting Started7.4 Specifying the Interfaces7.5 Defining the Top Level Design7.6 System Block Definitions and Interfaces7.7 The Camera Link Interface7.8 The PC Interface7.9 Summary
Chapter 8: Simple Embedded Processors
Abstract8.1 Introduction8.2 A Simple Embedded Processor8.3 A Simple Embedded Processor Implemented in VHDL8.4 A Simple Embedded Processor Implemented in Verilog8.5 Soft Core Processors on an FPGA8.6 Summary
Part 3: Designer’s Toolbox
Introduction
Chapter 9: Digital Filters
Abstract9.1 Introduction9.2 Converting S Domain to Z Domain9.3 Implementing Z Domain Functions in VHDL9.4 Basic Low Pass Filter Model9.5 Implementing Z Domain Functions in Verilog9.6 Finite Impulse Response Filters9.7 Infinite Impulse Response Filters9.8 Summary
Chapter 10: Secure Systems
Abstract10.1 Introduction to Block Ciphers10.2 Feistel Lattice Structures10.3 The Data Encryption Standard (DES)10.4 Advanced Encryption Standard10.5 Summary
Chapter 11: Memory
Abstract11.1 Introduction11.2 Modeling Memory in HDLs11.3 Read Only Memory11.4 Random Access Memory11.5 Synchronous RAM11.6 Flash Memory11.7 Summary
Chapter 12: PS/2 Mouse Interface
Abstract12.1 Introduction12.2 PS/2 Mouse Basics12.3 PS/2 Mouse Commands12.4 PS/2 Mouse Data Packets12.5 PS/2 Operation Modes12.6 PS/2 Mouse with Wheel12.7 Basic PS/2 Mouse Handler VHDL12.8 Modified PS/2 Mouse Handler VHDL12.9 Basic PS/2 Mouse Handler in Verilog12.10 Summary
Chapter 13: PS/2 Keyboard Interface
Abstract13.1 Introduction13.2 PS/2 Keyboard Basics13.3 PS/2 Keyboard Commands13.4 PS/2 Keyboard Data Packets13.5 PS/2 Keyboard Operation Modes13.6 Summary
Chapter 14: A Simple VGA Interface
Abstract14.1 Introduction14.2 Basic Pixel Timing14.3 Image Handling14.4 A VGA Interface in VHDL14.5 A VGA Interface in Verilog14.6 Summary
Chapter 15: Serial Communications
Abstract15.1 Introduction15.2 Manchester Encoding and Decoding15.3 Implementing the Manchester Encoding Scheme using VHDL15.4 Implementing the Manchester Encoding Scheme using Verilog15.5 NRZ (Non-Return-to-Zero) Coding and Decoding15.6 NRZI (Non-Return-to-Zero-Inverted) Coding and Decoding15.7 RS-23215.8 Universal Serial Bus15.9 Summary
Part 4: Optimizing Designs
Introduction
Chapter 16: Design Optimization
Abstract16.1 Introduction16.2 Techniques for Logic Optimization16.3 Improving Performance16.4 Critical Path Analysis16.5 Summary
Chapter 17: Behavioral Modeling in using HDLs
Abstract17.1 Introduction17.2 How to Go from RTL to Behavioral HDL Descriptions17.3 Implementing the Behavioral Model using VHDL17.4 Implementing the Behavioral Model using Verilog17.5 Summary
Chapter 18: Mixed Signal Modeling
Abstract18.1 Introduction18.2 Basic Modeling Approach for VHDL-AMS18.3 Introduction to VHDL-AMS18.4 VHDL-AMS Analog Pins: TERMINALS18.5 Mixed Domain Modeling18.6 VHDL-AMS Analog Variables: Quantities18.7 Simultaneous Equations in VHDL-AMS18.8 A VHDL-AMS Example: A DC Voltage Source18.9 A VHDL-AMS Example: Resistor18.10 Differential Equations in VHDL-AMS18.11 Mixed-Signal Modeling with VHDL-AMS18.12 A Basic Switch Model18.13 Basic VHDL-AMS Comparator Model18.14 Multiple Domain Modeling18.15 Introduction to Verilog-AMS18.16 Verilog-AMS: Analog ports18.17 Mixed Domain Modeling in Verilog-AMS18.18 Verilog-AMS Analog Variables18.19 Verilog-AMS Analog Equations18.20 A Verilog-AMS Example18.21 Differential Equations in Verilog-AMS18.22 Mixed Signal Modeling with Verilog-AMS18.23 Multiple Domain Modeling using Verilog-AMS18.24 Summary
Chapter 19: Design Optimization Example: DES
Abstract19.1 Introduction19.2 The Data Encryption Standard19.3 MOODS19.4 Initial Design19.5 Initial Synthesis19.6 Optimizing the Datapath19.7 Final Optimization19.8 Results19.9 Triple DES19.10 Comparing the Approaches19.11 Summary
Part 5: Fundamental Techniques
Introduction
Chapter 20: Latches, Flip-Flops, and Registers
Abstract20.1 Introduction20.2 Latches20.3 Flip-Flops20.4 Registers20.5 Summary
Chapter 21: ALU Functions
Abstract21.1 Introduction21.2 Logic Functions in VHDL21.3 Structural n-Bit Addition21.4 Logic Functions in Verilog21.5 Configurable n-Bit Addition21.6 Two’s Complement21.7 Summary
Chapter 22: Finite State Machines in VHDL and Verilog
Abstract22.1 Introduction22.2 State Transition Diagrams22.3 Implementing Finite State Machines in VHDL22.4 Implementing Finite State Machines in Verilog22.5 Testing the Finite State Machine Model22.6 Summary
Chapter 23: Fixed Point Arithmetic
Abstract23.1 Introduction23.2 Basic Fixed Point Types in VHDL23.3 Fixed Point Functions in VHDL23.4 Testing the VHDL Fixed Point Functions23.5 Fixed Point Types in Verilog23.6 Floating Point Types in Verilog23.7 Summary
Chapter 24: Counters
Abstract24.1 Introduction24.2 Basic Binary Counter using VHDL24.3 Simple Binary Counter using Verilog24.4 Synthesized Simple Binary Counter24.5 Shift Register24.6 The Johnson Counter24.7 BCD Counter24.8 Summary
Chapter 25: Decoders and Multiplexers
Abstract25.1 Decoders25.2 Multiplexers25.3 Summary
Chapter 26: Multiplication
Abstract26.1 Introduction26.2 Basic Binary Multiplication26.3 VHDL Unsigned Multiplier26.4 Synthesis of the Multiplication Function26.5 Simple Multiplication using VHDL26.6 Simple Multiplication using Verilog26.7 Summary
Chapter 27: Simple 7-Segment (LCD) Displays
Abstract27.1 Introduction27.2 VHDL LCD Module Decoder27.3 Verilog LCD Module Decoder27.4 Summary
Bibliography
IntroductionUseful Texts for VHDLUseful Texts for VerilogUseful Texts for FPGAsGeneral Digital Design Books
Index

Content preview from Design Recipes for FPGAs, 2nd Edition

Chapter 6

Synthesis

Abstract

This chapter introduces the key concept for modern FPGA design of synthesis. This process is the translation of a behavioral hardware description language representation into the low level bits that are programmed onto the hardware device. This chapter will review some of the design trade-offs commonly made between power, speed and area to ensure the design is functionally correct, and also optimized in the manner the designer requires.

Keywords

Synthesis

Optimization

Data path logic

6.1 Introduction

The original intention of hardware description languages was to have a design specification language for digital circuits. The main goal of the work was to have a design representation that could be simulated to test ...

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Design Recipes for FPGAs, 2nd Edition

by Peter Wilson

Synthesis

Abstract

6.1 Introduction

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