Design Recipes for FPGAs, 2nd Edition

Index

Note: Page numbers followed by f indicate figures and t indicate tables.

A

Accumulators 79–80

Advanced encryption standard (AES) 

byte substitution table 150, 150f

structure 148, 148f

VHDL model 151–163

AES  See Advanced encryption standard (AES)

ALU  See Arithmetic logic unit (ALU)

Architecture 18, 18f

declaration section 21

definition 20–21

statement section 21

Arithmetic logic unit (ALU) 

configurable n-bit addition 301–302

1-bit adder 297–299, 298f, 299f

structural n-bit addition 299–300

two’s complement 302–304

Verilog 105–107, 107f, 300–301

VHDL 89–90, 295–299

B

Baud clock generator 218–221, 218f

BCD counter  See Binary coded decimal (BCD) counter

Behavioral hardware description language 

RTL 237, 238f

Verilog module 240–242