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Designing SOCs with Configured Cores by Steve Leibson

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1.6. Increasing Processor Performance in the Micro World

Lacking the access to the high clock rates previously available to PC processor designers, processor core designers must turn to alternative performance-enhancing strategies. Use of additional buses and wider buses are both good performance-enhancing strategies for SOC-centric processor design. In the macro world of packaged microprocessors, additional processor pins incur a real cost. Packages with higher pin counts are more expensive, they’re harder to test, and they require more costly sockets. However, in the micro world of SOC design, additional pins for wider buses essentially cost nothing. They do incur some additional routing complexity, which may or may not increase design difficulty. ...

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