2.2. The ASIC Design Flow
SOC design is quite unlike board-level system design. There’s much less physical prototyping in the SOC world. Instead, SOC design verification relies almost exclusively on simulations. In fact, the SOC EDA design toolkit and ASIC design flow differ substantially from board-level design tools and flow. Figure 2.1, adapted from the Reuse Methodology Manual for System-on-a-Chip Design, presents a simplified view of the ASIC design flow called the “waterfall model” that was already showing its age when the manual was published in 1998.
Figure 2.1. This simplified representation of the ASIC design flow enumerates some of the steps required to transform a system specification into a chip layout.
The first box of the simplified ...
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